1200 Semiconductor Jobs - Page 3

Title: Lead Engineer Analog and Mixed Signal Design About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com . Introduction: GlobalFoundries is looking for highly motivated Analog and Mixed Signal Design Engineer to work in the Reference design team based in Bangalore. The successful candidate will work with 100% quality and minimal cycle time in mind. This role requires working closely with the internal design, layout teams, technology, test and product engineering teams. The roles and responsibilities will include the design, simulation and verification of analog circuit design blocks like BGR, LDO, OTA, Current mirrors Your Job: Sound foundation in Analog and Mixed signal circuit design in advanced silicon technologies Support silicon bring-up and characterization Participate in implementation & design/layout reviews Contribute with innovative ideas for addressing design problems Required Qualifications: MTech with more than 7 years experience or PhDs with 3 years experience from top tier institutes Applicant should have proficient knowledge of Analog circuit design and experience with EDA (Cadence, ADS) in silicon technologies SiGe and CMOS (bulk and SOI) Experience in analog blocks like OPAMP, OTA, Bandgap References (BGR), LDO, Biasing circuits with temperature compensation and mismatch aware circuit design Experience in layout and parasitic extraction Circuit design, Reliability analysis, Statistical analysis of circuits Must have good technical verbal and written communication skills and ability to work with cross functional teams Be able to collaborate with technical design leads on multiple concurrent projects Preferred Qualifications: Knowledge of SiGe and CMOS technology nodes 45/32/28nm and below is an advantage Hands-on knowledge of state-of-the-art analog design flows and knowledge of ADC, DACs is a plus Good publication and patent record Dedication and the ability to work within a very dynamic interdisciplinary environment Ability to communicate as well as work efficiently in an international multi-disciplinary environment. Exceptional spoken and written Proficiency in English Strong analytical and problem-solving skills. GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency, and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations. Information about our benefits you can find here: https: / / gf.com / about-us / careers / opportunities-asia

Title: Lead Engineer Analog and Mixed Signal Design About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com . Introduction: GlobalFoundries is looking for highly motivated Analog and Mixed Signal Design Engineer to work in the Reference design team based in Bangalore. The successful candidate will work with 100% quality and minimal cycle time in mind. This role requires working closely with the internal design, layout teams, technology, test and product engineering teams. The roles and responsibilities will include the design, simulation and verification of analog circuit design blocks like BGR, LDO, OTA, Current mirrors Your Job: Sound foundation in Analog and Mixed signal circuit design in advanced silicon technologies Support silicon bring-up and characterization Participate in implementation & design/layout reviews Contribute with innovative ideas for addressing design problems Required Qualifications: MTech with more than 7 years experience or PhDs with 3 years experience from top tier institutes Applicant should have proficient knowledge of Analog circuit design and experience with EDA (Cadence, ADS) in silicon technologies SiGe and CMOS (bulk and SOI) Experience in analog blocks like OPAMP, OTA, Bandgap References (BGR), LDO, Biasing circuits with temperature compensation and mismatch aware circuit design Experience in layout and parasitic extraction Circuit design, Reliability analysis, Statistical analysis of circuits Must have good technical verbal and written communication skills and ability to work with cross functional teams Be able to collaborate with technical design leads on multiple concurrent projects Preferred Qualifications: Knowledge of SiGe and CMOS technology nodes 45/32/28nm and below is an advantage Hands-on knowledge of state-of-the-art analog design flows and knowledge of ADC, DACs is a plus Good publication and patent record Dedication and the ability to work within a very dynamic interdisciplinary environment Ability to communicate as well as work efficiently in an international multi-disciplinary environment. Exceptional spoken and written Proficiency in English Strong analytical and problem-solving skills. GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency, and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations.

Validation engineer to work on automation tools for WIFI. Job Description Job Description As a Sr Staff Engineer , you will play a pivotal role in defining and implementing best practices for Wi-Fi validation. This role will involve working with cross-functional teams, including firmware developers, product managers, and test teams, to ensure that the Wi-Fi products meet the highest standards of performance, reliability, and interoperability across various environments. Your Profile You are best equipped for this task if you have: Engineering degree from a reputed college. 4 to 10 years of hands-on software testing & automation experience. Strong understanding of WLAN standards (IEEE 802.11 family). Strong problem-solving ability with a detail-oriented mindset. Excellent communication skills, both written and verbal. Interface with RF systems and integration teams on RF board layout, test interface methodology and programming sequence, and RF calibration programming. for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Learn more about our various contact channels. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

Applications are invited for the Post of Junior Research Fellow ( JRF ) for the ANRF Funded Project in the Department of Physics, School of Advanced Sciences (SAS), at Vellore Institute of Technology (VIT), Vellore, T.N, India. Title of the Project : “Development of cost-efficient and scalable perovskite based colloidal nanoparticles for high performance plastic scintillators” Qualification : M.Sc./ M.Tech. in Physics/ Materials Science or related fields from recognized universities/institutes with a minimum of first class and with GATE / CSIR-UGC JRF / NET-LS qualification. Mandatory Skills : Candidates should have a strong research background in synthesis and characterization of nanomaterials. Experience with colloidal semiconductor nanomaterials and related photo physics is desirable. Stipend : Rs. 37,000 p.m. + 8% HRA for the first two years (JRF); Rs. 42,000 p.m.+ 8% HRA for the third year (SRF) will be as per Institute norms. No. of Vacancies : 01 Post (ONE) Age Limit (if any) : Not exceeding 30 years i.e. Age must be from 18 to 30 years Sponsoring Agency : ANRF, PMECRG program, New Delhi, India Duration : 36 Months Principal Investigator : Dr. Abhinav Anand, Assi stant Professor, Department of Physics School of Advanced Sciences, Vellore Institute of Technology (VIT) Vellore - 632 014, Tamil Nadu. Interested candidates with the above-mentioned qualifications can send your resume along with relevant documents pertaining to the details of qualifications, scientific accomplishments, experience (if any) and latest passport size photo etc. on or before ( 18/08/2025) through the website: http://careers.vit.ac.in No TA and DA will be paid for appearing the interview. Shortlisted candidates will be called for an interview at a later date which will be intimated by email. The selected candidate will be expected to join at the earliest.

Join AISemiCon as a SerDes Engineer and drive the design and development of high-speed SerDes circuits for data communication. Collaborate with cross-functional teams to implement efficient and reliable SerDes architectures. We are looking for passionate individuals with expertise in SerDes design who enjoy tackling complex challenges. Responsibilities include defining and implementing SerDes architectures and collaborating with various teams. The key responsibilities for this role include, but are not limited to: Responsibilities Design of High Speed SERDES products on leading-edge technology nodes (FinFET or higher nodes) Design and development of SerDes IPs from specification (jitter budget, power budget, etc.) Interface with various engineering teams within the product line including verification, layout, validation, test, systems to successfully execute new products Participate in technical leadership of the team in the areas of circuit design and SERDES architectures. Collaborate with cross-functional teams to define and architect SerDes solutions for high-speed data communication applications. Design and develop high-speed SerDes circuits, including transmitters, receivers, equalizers, clock and data recovery (CDR), and analog front-end blocks. Conduct transistor-level design, simulation, and layout of SerDes blocks. Perform system-level verification and characterization of SerDes designs, including eye diagram analysis, jitter measurements, and link performance analysis. Work closely with the system engineering team to ensure the SerDes meets the performance requirements and specifications of the target applications. Drive innovation by exploring new SerDes techniques, circuit topologies, and emerging technologies. Collaborate with customers and partners to understand their requirements and provide customized SerDes solutions. Provide technical guidance and mentorship to junior members of the team. Stay updated with the latest advancements in SerDes design, industry standards, and emerging technologies. Qualifications (MTech/MS/PhD) with a minimum of 5-7 years of experience with High Speed SerDes analog design, and system architectures Design experience in some of the following High Speed SERDES circuit blocks: Driver, Receivers ( CTLE-DFE/ ADC based receivers ) , Phase Interpolators. Design of High Speed SERDES products on leading-edge technology nodes (FinFET or higher nodes) Design and development of SerDes IPs from specification (jitter budget, power budget, etc.) Low jitter PLL, High Speed Clock Distribution and modeling of digitally assisted analog adaptive loops Familiarity with CDR architectures Proficient at partitioning chip level requirements to specifications at the block level. Strong written and verbal communication skills. Proactive, collaborative, and creative approach to innovation, technical development and consensus facilitation to influence optimal project results. Strong team player. Ability to function independently, be self-driven. Applied Intelligence Semiconductors Private Limited (AISemiCon), an Innovative Product Enterprise is founded by seasoned semiconductor professionals, envisioned to deliver cutting edge products for the globe. At our company, we provide an innovative and collaborative workplace environment that empowers talented individuals to make a significant impact on the future of the semiconductor industry. We look forward to reviewing your application and discussing how you can contribute to our mission of advancing high-performance computing. Note: This job description provides a general overview of the responsibilities and requirements for the position and may be subject to change based on business needs. Apply for this position Allowed Type(s): .pdf By using this form you agree with the storage and handling of your data by this website. *

As an Architect SoC at AISemiCon, you will be responsible for designing and architecting complex system-on-chip (SoC) solutions for a range of applications, including IoT, automotive, 5G, and high-performance computing (HPC). You will collaborate with cross-functional teams, including hardware, software, and verification engineers, to define and implement SoC architectures that meet the project requirements. We are seeking individuals who have a passion for innovation and are excited about the opportunity to create products from scratch. The key responsibilities for this role include, but are not limited to: Key Responsibilities: Collaborate with cross-functional teams to define and architect SoCs for various applications, such as IoT, automotive, 5G, and HPC. Conduct feasibility studies and performance analysis to determine optimal SoC architectures, subsystems, and interfaces. Develop and review specifications, microarchitecture, and system-level design documentation for SoCs. Work closely with hardware and software teams to ensure successful integration and functionality of the SoCs. Drive innovation by exploring new technologies, methodologies, and industry trends relevant to SoC design. Optimize SoC designs for power, performance, area, and other key metrics. Collaborate with customers and partners to understand their requirements and provide SoC solutions that meet their needs. Provide technical guidance and mentorship to junior members of the team. Stay updated with the latest advancements in SoC design and emerging industry standards. Qualifications: Bachelor s, Master s, or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in SoC architecture and design. Expertise in one or more application domains, such as IoT, automotive, 5G, or HPC. Strong understanding of hardware and software interactions in SoCs. Proficiency in industry-standard design and verification tools. Solid knowledge of system-level trade-offs and constraints, including power, performance, area, and latency. Excellent problem-solving, analytical, and communication skills. Ability to work effectively in a collaborative team environment. Applied Intelligence Semiconductors Private Limited (AISemiCon), an Innovative Product Enterprise is founded by seasoned semiconductor professionals, envisioned to deliver cutting edge products for the globe. At our company, we provide an innovative and collaborative workplace environment that empowers talented individuals to make a significant impact on the future of the semiconductor industry. We look forward to reviewing your application and discussing how you can contribute to our mission of shaping the future of semiconductor technology. Note: This job description provides a general overview of the responsibilities and requirements for the position and may be subject to change based on business needs. Apply for this position Allowed Type(s): .pdf By using this form you agree with the storage and handling of your data by this website. *

As an Architect CPU at AISemiCon, you will play a vital role in designing and architecting high-performance and energy-efficient central processing units (CPUs). You will collaborate with cross-functional teams, including microarchitecture, verification, and software teams, to define and develop state-of-the-art CPU architectures. We are seeking individuals who are passionate about CPU design, have a deep understanding of microarchitecture, and enjoy solving complex challenges. The key responsibilities for this role include, but are not limited to: Key Responsibilities: Collaborate with cross-functional teams to define and architect CPU microarchitecture for next-generation semiconductor products. Conduct feasibility studies, performance analysis, and power modeling to determine optimal CPU architectures and design choices. Develop and review specifications, microarchitecture, and RTL designs for CPUs. Work closely with the design and verification teams to ensure successful implementation and integration of CPUs. Optimize CPU designs for performance, power efficiency, and area. Collaborate with software teams to ensure seamless software-hardware integration and optimize CPU performance. Explore new technologies, methodologies, and industry trends in CPU design to drive innovation and enhance performance. Provide technical guidance and mentorship to junior members of the team. Collaborate with customers and partners to understand their requirements and provide CPU solutions that meet their needs. Stay updated with the latest advancements in CPU architecture and emerging industry standards. Qualifications: Bachelor s, Master s, or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in CPU architecture and design. Strong understanding of microarchitecture concepts, including pipeline design, cache subsystems, branch prediction, and out-of-order execution. Proficiency in industry-standard design and verification tools. Solid knowledge of system-level trade-offs and constraints, including performance, power, area, and latency. Experience with instruction set architecture (ISA) design and optimization is a plus. Excellent problem-solving, analytical, and communication skills. Ability to work effectively in a collaborative team environment. Applied Intelligence Semiconductors Private Limited (AISemiCon), an Innovative Product Enterprise is founded by seasoned semiconductor professionals, envisioned to deliver cutting edge products for the globe. At our company, we provide an innovative and collaborative workplace environment that empowers talented individuals to make a significant impact on the future of the semiconductor industry. We look forward to reviewing your application and discussing how you can contribute to our mission of revolutionizing semiconductor technology. Note: This job description provides a general overview of the responsibilities and requirements for the position and may be subject to change based on business needs. Apply for this position Allowed Type(s): .pdf By using this form you agree with the storage and handling of your data by this website. *

The Solution Owner manages the implementation of change requests and coordinates the respective work packages of the Solution Developers and is responsible for the continuous quality assurance to contribute to overall service improvement and ensure compliance. Job Description In your new role you will: Candidate will be solution owner for Infineon s i2/JDA/Blue Yonder S&OP/SNOP/SOP implementation and will be responsible for overall lifecycle of the relevant applications. He/she ensures the release of application/software from the technical point of view and approves general usage and manages relationships with (business) stakeholders and respective communication for dependent/related application/software. The Solution Owner manages the implementation of change requests and coordinates the respective work packages of the Solution Developers. He/she delivers/implements released changes within the organization by conducting the relevant tests as well as business change management and end-user knowledge management. The Solution Owner is responsible for the continuous quality assurance to contribute to overall service improvement and ensure compliance. Key Responsibilities and Tasks include Manage relationships to the end-user communities and Ensure consistent communication on changes and the respective end-user knowledge management Manage the releases of solutions as well as change requests and coordinate respective activities Ensure continuous quality assurance and drive improvement on application level Your Profile You are best equipped for this task if you have: Blue Yonder/JDA/i2 experience in Manufacturing or Semiconductor environment with 1 full life-cycle implementation Experience with Version 9.0 or later. 1+ years of experience on JDA S&OP/JDA SNOP/JDA SOP 1+ years of experience with JDA SCPO Good problem-solving skills and out of the box thinking Ability to understand and communicate complex logics with different internal stakeholders Sound knowledge of and experience working with Software Lifecycle Management and concepts Sound knowledge of and experience working with databases and related concepts Hands on experience of working on PL/SQL procedures and scripting Hands on experience with Unix/Linux Commands & Shell Scripts, Windows Batch Scripts Should be familiar with integration of S&OP modules (inbound & outbound) Contact: Pooja.AnandaChowta@infineon.com We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Learn more about our various contact channels. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

As a SoC Architect 5G at AISemiCon, you will play a crucial role in designing and architecting system-on-chip (SoC) solutions tailored for 5G applications. You will collaborate closely with cross-functional teams, including hardware, software, and verification teams, to define and implement SoC architectures that meet the unique requirements of 5G wireless systems. We are seeking individuals who have a strong passion for 5G technology, possess deep expertise in SoC design, and are excited about creating innovative solutions from scratch. The key responsibilities for this role include, but are not limited to: Key Responsibilities: Collaborate with cross-functional teams to define and architect SoCs optimized for 5G wireless communication applications. Conduct feasibility studies and performance analysis to determine optimal SoC architectures, subsystems, and interfaces for 5G systems. Develop and review specifications, microarchitecture, and system-level design documentation for 5G-focused SoCs. Work closely with hardware and software teams to ensure successful integration and functionality of the SoCs. Drive innovation by exploring new technologies, methodologies, and industry trends relevant to 5G and SoC design. Optimize SoC designs for high data throughput, low latency, power efficiency, and other key metrics specific to 5G applications. Collaborate with customers and partners to understand their requirements and provide SoC solutions that meet their 5G connectivity needs. Provide technical guidance and mentorship to junior members of the team. Stay updated with the latest advancements in SoC design for 5G and emerging industry standards. Qualifications: Bachelor s, Master s, or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in SoC architecture and design, with a specific focus on 5G applications. Deep understanding of hardware and software interactions in SoCs and the unique requirements of 5G wireless systems. Proficiency in industry-standard design and verification tools. Solid knowledge of system-level trade-offs and constraints in areas such as power, performance, area, and latency. Familiarity with wireless communication protocols, such as 5G NR, mmWave, and beamforming, is highly desirable. Excellent problem-solving, analytical, and communication skills. Ability to work effectively in a collaborative team environment. Applied Intelligence Semiconductors Private Limited (AISemiCon), an Innovative Product Enterprise is founded by seasoned semiconductor professionals, envisioned to deliver cutting edge products for the globe. At our company, we provide an innovative and collaborative workplace environment that empowers talented individuals to make a significant impact on the future of the semiconductor industry. We look forward to reviewing your application and discussing how you can contribute to our mission of driving the evolution of 5G wireless communication. Note: This job description provides a general overview of the responsibilities and requirements for the position and may be subject to change based on business needs. Apply for this position Allowed Type(s): .pdf By using this form you agree with the storage and handling of your data by this website. *

As a SoC Architect HPC at AISemiCon, you will be responsible for designing and architecting system-on-chip (SoC) solutions optimized for high-performance computing applications. Collaborating closely with cross-functional teams, including hardware, software, and verification, you will define and implement SoC architectures that meet the unique requirements of HPC systems. We are seeking individuals who are passionate about HPC, possess deep expertise in SoC design, and thrive in solving complex challenges. The key responsibilities for this role include, but are not limited to: Key Responsibilities: Collaborate with cross-functional teams to define and architect SoCs optimized for high-performance computing applications. Conduct feasibility studies, performance analysis, and power modeling to determine optimal SoC architectures, subsystems, and interfaces for HPC systems. Develop and review specifications, microarchitecture, and system-level design documentation for HPC-focused SoCs. Work closely with hardware and software teams to ensure successful integration and functionality of the SoCs. Drive innovation by exploring new technologies, methodologies, and industry trends relevant to HPC and SoC design. Optimize SoC designs for high computational performance, memory bandwidth, power efficiency, and other key metrics specific to HPC applications. Collaborate with customers and partners to understand their requirements and provide SoC solutions that meet their HPC needs. Provide technical guidance and mentorship to junior members of the team. Stay updated with the latest advancements in SoC design for HPC and emerging industry standards. Qualifications Bachelor s, Master s, or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in SoC architecture and design, with a specific focus on high-performance computing applications. Deep understanding of hardware and software interactions in SoCs and the unique requirements of HPC systems. Proficiency in industry-standard design and verification tools. Solid knowledge of system-level trade-offs and constraints in areas such as power, performance, area, and latency. Familiarity with parallel computing architectures, accelerators, and memory hierarchies is highly desirable. Excellent problem-solving, analytical, and communication skills. Ability to work effectively in a collaborative team environment. Applied Intelligence Semiconductors Private Limited (AISemiCon), an Innovative Product Enterprise is founded by seasoned semiconductor professionals, envisioned to deliver cutting edge products for the globe. At our company, we provide an innovative and collaborative workplace environment that empowers talented individuals to make a significant impact on the future of the semiconductor industry. We look forward to reviewing your application and discussing how you can contribute to our mission of advancing high-performance computing. Note: This job description provides a general overview of the responsibilities and requirements for the position and may be subject to change based on business needs. Apply for this position Allowed Type(s): .pdf By using this form you agree with the storage and handling of your data by this website. *

The impact you ll make As a Software Engineer at Lam, you will be at the forefront of innovation by designing, developing, and troubleshooting, and debugging software programs. Your role is pivotal in developing software tools that support design, infrastructure, and technology platforms. Your expertise will determine hardware compatibility and influence design, ensuring seamless integration between software and hardware. In this role, you ll make an impact across Lam s entire product portfolio of equipment working within our centralized software engineering team, collaborating with some of the brightest minds in the industry. What you ll do Design, develop, troubleshoot, and debug software programs for enhancements and new products. Implement new customer requirements and features in our existing application. Maintain and enhance existing code base by investigating and resolving problem areas. Demonstrate, clearly communicate, and present solutions through clear documentation, flowcharts, and well-structured code. Collaborate with cross functional teams to design and develop software programs. Provide technical guidance and mentoring for more junior engineers. May visit customer site to provide support and have ability to travel (total is less than 10%). Who we re looking for Eligibility Criteria: Years of Experience: 7 - 10 Years Educational qualification: Bachelor s or Master s degree in Engineering (Preferably Computer Science, Information tech, E&E, E&C, Telecom or Instrumentation Technology) Primary Responsibilities: Responsible for the design, development, and maintenance of LAM standards compliant software Plans, coordinates, and executes development activities within small to medium-sized projects Responsible for leading and driving projects involving multiple developers from within and other departments by taking complete ownership of component software Responsible for maintenance of install base by analyzing, debugging and fixing customer issues Participates in customer issues and escalations to provide quick workarounds and long-term fixes Responsible for technically reviewing and mentoring junior engineers with the object to deliver high quality software on time Interact with peers across teams to carry out day to day activities Initiates and drives continuous improvement projects aimed at improving productivity enabling business units deliver products with minimum cost and shortest cycle time Drives productivity of the group by monitoring and reporting KPIs and driving necessary actions to address any gaps Skills Mandatory Skills: Programming knowledge in C preferably in hardware interfacing Knowledge of RTOS Experience in SDLC Participated in design, IM and testing of projects Strong analytical, logical, trouble shooting skills Excellent problem solving and decision-making skills Hands on experience in complete project development life cycle Exposure to customer management Desirable Skills: Knowledge of OOPS concepts, Scripting Experience in the semiconductor equipment manufacturing industry Understanding of distributed systems and socket programming Excellent communication and Presentation skills Our commitment We believe it is important for every person to feel valued, included, and empowered to achieve their full potential. By bringing unique individuals and viewpoints together, we achieve extraordinary results. Lam Research ("Lam" or the "Company") is an equal opportunity employer. Lam is committed to and reaffirms support of equal opportunity in employment and non-discrimination in employment policies, practices and procedures on the basis of race, religious creed, color, national origin, ancestry, physical disability, mental disability, medical condition, genetic information, marital status, sex (including pregnancy, childbirth and related medical conditions), gender, gender identity, gender expression, age, sexual orientation, or military and veteran status or any other category protected by applicable federal, state, or local laws. It is the Companys intention to comply with all applicable laws and regulations. Company policy prohibits unlawful discrimination against applicants or employees. Lam offers a variety of work location models based on the needs of each role. Our hybrid roles combine the benefits of on-site collaboration with colleagues and the flexibility to work remotely and fall into two categories On-site Flex and Virtual Flex. On-site Flex you ll work 3+ days per week on-site at a Lam or customer/supplier location, with the opportunity to work remotely for the balance of the week. Virtual Flex you ll work 1-2 days per week on-site at a Lam or customer/supplier location, and remotely the rest of the time.

We empower smarter business operations by connecting equipment, software, and services to protect, control and optimize assets within electrical infrastructures. The business provides customers, across various industries, with end-to-end product and service solutions ensuring the reliability and protection of their electrical infrastructure. We provide the latest industry insights and technology to develop solutions needed to meet customers evolving challenges, including innovative critical power solutions designed for high reliability and performance. Our culture is one of quality and operational excellence fueled and supported by talented people, tools and processes, and expertise. To return to the OmniOn Power website, click here. Job Overview: Lead and transform OmniOn Powers India sales organization to drive aggressive revenue growth to $55M by 2028. Develop and execute go-to-market strategies that position OmniOn as the leading power solutions provider for Indias booming 5G infrastructure, data center expansion, and electric vehicle charging markets. Lead a high-performing sales organization of Regional Sales Managers This is a business transformation role with rewarding career growth for exceptional performers. This position reports to OmniOn Powers India Region Leader and is based in Bangalore, India. Responsibilities: As the India Sales Manager Leader, you will: In alignment with the Region Leader, develop and execute comprehensive sales strategy including specific strategic sales and marketing initiatives for 5G infrastructure, data centers, EV charging, and industrial applications. Plan and implement annual budgets targeting aggressive revenue growth over 3 years across all sub-regions within India. Define key marketing and sales targets (volume, pricing, portfolio mix, channel coverage, market penetration) with specific focus on telecom tower infrastructure (25k+ annual installations), data center power solutions, and EV charging networks. Establish appropriate metrics and measurement tools to monitor performance and market share gains. Working with the Region Leader, coordinate alignment and support from regional marketing, customer service, business development, quotations, operations and R&D to support execution of Indias commercial strategy. Drive product localization requirements, timing and custom solution development requirements for the India region. Ensure achievement of aggressive KPIs including $25M+ revenue (Year 1), design wins with major telecom operators and data center companies, SFDC pipeline accuracy above 90%, and maintain gross margins above company targets. Monitor, analyze regional performance against BSNL tower deployments, Reliance infrastructure projects, and emerging EV charging networks. Manage selling expenses to budget while investing strategically in market development, trade shows (Electronica, India Mobile Congress), technical seminars, and customer relationship building activities. Develop and implement key account strategies for major customers including telecom operators (BSNL, Bharti, Reliance), data center operators, and EV infrastructure companies. Conduct annual account reviews and identify strategic expansion opportunities within existing customer base. Lead customer engagement activities including C-level presentations, technical consultations, and solution development sessions. Maintain deep understanding of market trends in 5G power requirements, AI/ML data center demands, and EV charging infrastructure needs. Drive accurate demand forecasting through robust SFDC utilization, ensuring pipeline visibility supports aggressive revenue targets and manufacturing planning. Implement advanced sales analytics and competitive intelligence gathering. Build and scale sales organization capability through strategic hiring, advanced sales training (Miller Heiman methodology), and performance management. Develop succession planning for key roles and create career advancement pathways. Act as customer advocate and market voice to global organization, identifying product enhancement opportunities, pricing strategies, and competitive positioning requirements specific to Indian market dynamics. Collaborate with HRBP and training manager to implement comprehensive development programs for sales professionals, including technical product training, consultative selling skills, and industry expertise development. Lead business development initiatives with distribution partners, system integrators, and OEM partners. Negotiate strategic partnerships that expand market reach and accelerate revenue growth across target segments. Eligibility Requirements: OmniOn Power will only employ those who are legally authorized to work in India for this opening. We will not sponsor individuals for employment visas, now or in the future, for this job opening. Basic Qualifications: Bachelor s degree in Engineering AND 10 years of commercial experience with minimum 5 years leading sales teams in electronics, semiconductor, or power conversion domains with demonstrated revenue responsibility of $15M+. Position requires ability to travel average of 50% of time during typical work week, predominantly domestic travel across India to key customer locations. Minimum of 2 years experience in Key Account Management with proven track record managing relationships with large telecom operators, data center companies, or industrial OEMs. Minimum of 2 years experience in both OEM flow sales model, demonstrating ability to navigate complex decision-making units and extended sales cycles. Proven track record of building and scaling sales teams, with experience managing strong revenue growth in competitive electronics markets. Desired Characteristics: Masters degree in Engineering, Business Administration (MBA), or related field with focus on technology markets and business strategy. Experience managing distribution partners in electronics power space OR experience working at distributor in power electronics industry, with demonstrated success in channel development and partner enablement. Strong managerial and leadership skills with ability to interpret and forecast changes in customers buying patterns, anticipate market shifts in 5G/data center/EV segments, and evaluate competitive positioning against international and domestic suppliers. Deep knowledge of power conversion technologies including DC/DC converters, rectifiers, and power systems architecture, with ability to develop technical solution strategies and communicate product enhancement requirements to engineering teams. Exceptional communication and presentation skills with proven ability to negotiate complex deals with C-level executives, influence buying decisions in enterprise sales environments, and represent company at industry forums and trade shows. Demonstrated financial knowledge of P&L, margin optimization, pricing strategy development, and budget management in high-growth technology environments. Existing relationships within Indias telecom infrastructure ecosystem (tower companies, operators, system integrators), data center industry, or EV charging network developers. Experience collaborating with global headquarters organizations and matrix management structures, with ability to influence cross-functional teams and drive alignment across geographies. We are an Equal Employment Opportunity Employer (EEO). All qualified applicants will receive consideration for employment without regard to their race, creed, color, ancestry, religion, sex, national origin, citizen status, age, sexual orientation, gender identity, disability, marital status, family medical leave status, or protected veterans status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

As an Analog Layout Engineer at AISemiCon, you will play a critical role in the design and development of high-performance analog and mixed-signal integrated circuits (ICs). Your main responsibility will be to create layout designs for analog blocks and ensure their adherence to design rules, specifications, and performance targets. You will collaborate closely with cross-functional teams, including circuit designers, verification engineers, and process engineers, to achieve optimal layout implementation. We are seeking individuals with a strong passion for analog layout, deep expertise in IC design, and a keen eye for detail. The key responsibilities for this role include, but are not limited to: Requirements: Excellent work experience in Analog Layout design in advanced node processes Hands on experience in any or multiple critical blocks such as BGR, LDO, Charge pump, SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Current Mirrors, Comparator, Differential Amplifier etc. Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process Excellent understanding of Analog Layout concepts (e.g. Matching, Electro- migration, Latch-up, Coupling, Cross-talk, IR-drop, Active and Passive parasitic devices etc. Excellent problem-solving skills in Routing Congestion, Physical Verification in Custom Layout. Work closely with the verification team to address layout-related issues and ensure design robustness. Follow design rules, guidelines, and best practices to ensure design manufacturability and yield. Collaborate with process engineers to understand process requirements and optimize layout designs accordingly. Conduct layout parasitic extraction and work with the simulation team to validate and optimize design performance. Participate in design reviews and contribute to overall design improvements. Stay updated with the latest advancements in analog layout techniques, process technologies, and industry standards. Qualifications: Bachelor s, Master s, or Ph.D. degree in Electrical Engineering or a related field. 7-8 Years of proven experience in analog layout design, with expertise in IC design methodologies and tools. Sound knowledge and experience for verification checks like DRC / LVS / ERC / Antenna / LPE / DFM etc. Knowledge of various analog layout techniques, understanding of various circuit principles as affected by Layouts such as speed, capacitance, power, noise, and area Proficiency in industry-standard layout tools, such as Cadence Virtuoso or Synopsys IC Compiler and verification tools in a Linux environment of Cadence EDA tools. Solid understanding of layout design principles, design rules, and process technologies. Familiarity with analog block-level and top-level layout techniques for performance optimization. Knowledge of layout parasitic extraction and simulation methodologies. Excellent attention to detail and problem-solving skills. Effective communication and collaboration skills to work in a cross-functional team environment. Applied Intelligence Semiconductors Private Limited (AISemiCon), an Innovative Product Enterprise is founded by seasoned semiconductor professionals, envisioned to deliver cutting edge products for the globe. At our company, we provide an innovative and collaborative workplace environment that empowers talented individuals to make a significant impact on the future of the semiconductor industry. We look forward to reviewing your application and discussing how you can contribute to our mission of advancing high-performance computing. Note: This job description provides a general overview of the responsibilities and requirements for the position and may be subject to change based on business needs. By using this form you agree with the storage and handling of your data by this website. *

Power Management IC Design (PMIC) More Details Power Management IC Design (PMIC) AISEMICON The Analog Design Engineer will lead the design of Power Management IC products. We are looking for a person who possesses technical expertise in DC-DC converters (Buck/Boost). Experience of Power Management IC design / knowledge of Power converters architecture is must requirement for this role. Responsibilities Development of Power Management Products with emphasis on switching converters Buck, Boost and LDO design. Knowledge of Power converter architectures Buck, Boost etc. Thorough knowledge of Analog design- OpAmp, Comparators, Bandgap References, Oscillators etc. Responsible to architecture and analysis for control loops Responsible for analog design, IC floor plan, integration and layout supervision through all stages of IC development Qualifications: Masters/PhD in Electronics/VLSI Understanding of process technologies and device behavior which are important for high voltage, high power operation and reliability issues. 5-7 years of experience. Strong written and verbal communication skills. Proactive, collaborative, and creative approach to innovation, technical development and consensus facilitation to influence optimal project results. Strong team player. Ability to function independently, be self-driven Applied Intelligence Semiconductors Private Limited (AISemiCon), an Innovative Product Enterprise is founded by seasoned semiconductor professionals, envisioned to deliver cutting edge products for the globe. At our company, we provide an innovative and collaborative workplace environment that empowers talented individuals to make a significant impact on the future of the semiconductor industry. We look forward to reviewing your application and discussing how you can contribute to our mission of advancing high-performance computing. Note: This job description provides a general overview of the responsibilities and requirements for the position and may be subject to change based on business needs. Apply for this position Allowed Type(s): .pdf By using this form you agree with the storage and handling of your data by this website. *

Data Converters (ADC/DAC) and PLL More Details Data Converters (ADC/DAC) and PLL AISEMICON As a Senior Analog/Mixed-Signal Design Engineer at AISemiCon, you will play a crucial role, focusing on high-performance analog- to-digital and digital-to-analog converters and PLL. The successful candidate in this role will do architecture, transistor level design starting from initial specification, through design and layout supervision. We are seeking individuals who have a strong passion for analog and mixed-signal design, possess deep expertise in Data Converters and PLLs, and thrive in solving complex challenges. The key responsibilities for this role include, but are not limited to: Responsibilities: High-performance analog or mixed-signal IC development in advanced CMOS processes Thorough familiarity with high-speed, high-resolution analog-to-digital (ADC) or digital-to-analog (DAC) data converter design techniques. Collaborate with cross-functional teams to define and architect Data Converter (ADC/DAC) and PLL solutions for high-speed data acquisition and timing generation applications. Design and develop high-performance analog and mixed-signal circuits, including Data Converters and PLLs. Conduct transistor-level design, simulation, and layout of Data Converter and PLL blocks. Perform system-level verification and characterization of Data Converter and PLL designs, including performance analysis, noise analysis, and timing verification. Work closely with the system engineering team to ensure the Data Converter and PLL designs meet the performance requirements and specifications of the target applications. Drive innovation by exploring new techniques, circuit topologies, and emerging technologies in Data Converters and PLLs. Collaborate with customers and partners to understand their requirements and provide customized solutions. Provide technical guidance and mentorship to junior members of the team. Stay updated with the latest advancements in Data Converter and PLL design, industry standards, and emerging technologies. Qualifications: 5-7 years of experience in designing high performance building block circuits such as Bandgap reference, op-amp, comparators, oscillators, DLL, PLL etc. Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis Experience with analog and digital behavioral modeling, and/or synthesis of digital control blocks Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools MATLAB understanding would be an added advantage Deep understanding of Data Converter architectures, analog-to-digital and digital-to-analog conversion techniques, and PLL principles. Proficiency in industry-standard EDA tools for IC design, simulation, and layout. Solid knowledge of system-level trade-offs and constraints in areas such as resolution, speed, power consumption, noise, and jitter. Experience with Data Converter and PLL characterization, validation, and debugging. Excellent problem-solving, analytical, and communication skills. Ability to work effectively in a collaborative team environment. Applied Intelligence Semiconductors Private Limited (AISemiCon), an Innovative Product Enterprise is founded by seasoned semiconductor professionals, envisioned to deliver cutting edge products for the globe. At our company, we provide an innovative and collaborative workplace environment that empowers talented individuals to make a significant impact on the future of the semiconductor industry. We look forward to reviewing your application and discussing how you can contribute to our mission of advancing high-performance computing. Note: This job description provides a general overview of the responsibilities and requirements for the position and may be subject to change based on business needs. By using this form you agree with the storage and handling of your data by this website. *

As an Architect SoC Architects Automation at AISemiCon, you will be responsible for designing and architecting system-on-chip (SoC) solutions tailored for automation applications. You will collaborate closely with cross-functional teams, including hardware, software, and verification teams, to define and implement SoC architectures that meet the unique requirements of automation systems. We are seeking individuals who have a strong passion for automation, possess deep expertise in SoC design, and are excited about creating innovative solutions from scratch. The key responsibilities for this role include, but are not limited to: Key Responsibilities: Collaborate with cross-functional teams to define and architect SoCs optimized for automation applications. Conduct feasibility studies and performance analysis to determine optimal SoC architectures, subsystems, and interfaces for automation systems. Develop and review specifications, microarchitecture, and system-level design documentation for automation-focused SoCs. Work closely with hardware and software teams to ensure successful integration and functionality of the SoCs. Drive innovation by exploring new technologies, methodologies, and industry trends relevant to automation and SoC design. Optimize SoC designs for real-time processing, low-latency communication, and reliability considerations specific to automation applications. Collaborate with customers and partners to understand their requirements and provide SoC solutions that meet their automation needs. Provide technical guidance and mentorship to junior members of the team. Stay updated with the latest advancements in SoC design for automation and emerging industry standards. Qualifications: Bachelor s, Master s, or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in SoC architecture and design, with a specific focus on automation applications. Deep understanding of hardware and software interactions in SoCs and the unique requirements of automation systems. Proficiency in industry-standard design and verification tools. Solid knowledge of system-level trade-offs and constraints in areas such as power, performance, area, and latency. Familiarity with communication protocols, real-time operating systems, and hardware acceleration techniques for automation is highly desirable. Excellent problem-solving, analytical, and communication skills. Ability to work effectively in a collaborative team environment. We look forward to reviewing your application and discussing how you can contribute to our mission of revolutionizing automation through semiconductor technology. Note: This job description provides a general overview of the responsibilities and requirements for the position and may be subject to change based on business needs. Apply for this position Allowed Type(s): .pdf By using this form you agree with the storage and handling of your data by this website. *

We are seeking highly skilled and motivated System-on-Chip (SoC) Performance and Power modeling (PnP) Architects to join our diverse team at Arm! Our team focuses on PnP Analysis of Arm SoCs/SoPs (System-on-Package), System level infrastructure (SoC/SoP/Rackscale/Podscale) build together in pre- and post- silicon environments. Working closely with design teams and customers, we develop best-in-class silicon platforms across markets such as servers, accelerators, client, infrastructure, IoT, and automotive. Responsibilities: Efficiently drive and resolve architectural investigations and PnP tradeoff studies across various SoC (CPU, GPU, NPU, Media, IO, interconnects, memory controllers) and Platform components. Perform detailed workload characterization to identify performance bottlenecks and propose architectural solutions. Collaborate, coordinate, and drive consensus across architects, and IP teams. Conduct workload compaction to facilitate effective modeling. Create profiling and visualization frameworks to analyze with right level of abstraction. Contribute to automation for streamlining production processes Stay up-to-date on latest advancements in application development, workload characterization, and performance/power/thermal analysis Required Skills and Experience : Experience (+8 years) in SoC Performance Modeling and analysis in the semiconductor industry. A background in Electrical Engineering, Computer Engineering, or Computer Science with an expertise in computer architecture, and microarchitecture. Understanding of general-purpose CPU/GPU microarchitecture, including knowledge of areas such as processor pipelines, caches, and memory hierarchy. Proficient in C/C++ for programming for large-scale software development, familiarity with SystemC TLM, and Python scripting language skills. Excellent communication, and interpersonal skills with ability to convey effectively complicated solutions. Drive PnP analysis as an experienced SoC Performance and Power modeling Architect at Arm, focusing on diverse silicon platforms Nice To Have Skills and Experience : Knowledge of interconnect micro-architecture design, PCIe/CXL and CHI protocols. Understanding of workloads used for performance optimization under system constraints (TDP, Limits). Ability to work in a fast-paced environment with changing priorities and requirements Experience with Unix, scripting, and source control systems (e.g., Git, Subversion). In Return: We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding! Partner and customer focus Teamwork and communication Creativity and innovation Team and personal development Impact and influence Deliver on your promises Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arm s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm

We are seeking a highly motivated and talented Software Development Engineer with background in database management to join our team at Sandisk. In this role, you will play a key role in the development and maintenance of our digital twin platform and database infrastructure. Key responsibilities include: Design and implement efficient data pipelines to enable seamless information flow within the digital twin platform, including simulators and storage systems. Establish database linkages across platforms, optimizing data structures for scalability and performance to manage large data volumes effectively. Develop ETL (Extract, Transform, Load) pipelines to process raw data into analysis-ready formats.. Leverage machine learning and data analytics techniques to optimize the design and manufacturing process, develop design recommendation systems, identify anomalies, and support failure analysis. Qualifications REQUIRED: MS Degree in Computer Science, Statistics, Mathematics, Data Science, or related quantitative/engineering field plus >3 years of relevant industrial experience Proven experi

IP Architect CXL / UCIe / USB / DDR / HBM, RISC-V CPU, NoC More Details IP Architect CXL / UCIe / USB / DDR / HBM, RISC-V CPU, NoC AISEMICON Job Description: As an IP Architect at AISemiCon, you will be responsible for designing and architecting intellectual property solutions for various industry standards and architectures. We are seeking IP architects with expertise in either CXL, UCIe, USB, DDR, HBM, RISC-V CPU, and or NoC to join our team. You will collaborate closely with cross-functional teams, including hardware, software, and verification, to define and develop IP solutions that meet the requirements of our customers. We are looking for individuals who are passionate about IP design, possess deep technical expertise, and thrive in solving complex challenges. The key responsibilities for this role include, but are not limited to: Key Responsibilities: Collaborate with cross-functional teams to define and architect IP solutions for industry standards and architectures respectively, such as CXL, UCIe, USB, DDR, HBM, RISC-V CPU, and NoC. Conduct feasibility studies and performance analysis to determine optimal IP architectures and specifications. Design and review IP specifications, microarchitecture, and system-level documentation. Work closely with the implementation team to ensure successful integration and functionality of the IP solutions. Drive innovation by exploring new technologies, methodologies, and industry trends relevant to IP design. Collaborate with customers and partners to understand their requirements and provide customized IP solutions. Provide technical guidance and mentorship to junior members of the team. Stay updated with the latest advancements in IP design, industry standards, and emerging technologies. Qualifications: Bachelor s, Master s, or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in IP architecture and design, with expertise in industry standards and architectures such as CXL, UCIe, USB, DDR, HBM, RISC-V CPU, and NoC. Deep understanding of hardware and software interactions in IP design and the unique requirements of industry standards. Proficiency in industry-standard design and verification tools. Solid knowledge of system-level trade-offs and constraints in areas such as power, performance, area, and latency. Excellent problem-solving, analytical, and communication skills. Ability to work effectively in a collaborative team environment. Applied Intelligence Semiconductors Private Limited (AISemiCon), an Innovative Product Enterprise is founded by seasoned semiconductor professionals, envisioned to deliver cutting edge products for the globe. At our company, we provide an innovative and collaborative workplace environment that empowers talented individuals to make a significant impact on the future of the semiconductor industry. We look forward to reviewing your application and discussing how you can contribute to our mission of providing cutting-edge semiconductor IP solutions. Note: This job description provides a general overview of the responsibilities and requirements for the position and may be subject to change based on business needs. Apply for this position Allowed Type(s): .pdf By using this form you agree with the storage and handling of your data by this website. *

We are seeking highly skilled and motivated System-on-Chip (SoC) Performance and Power modeling (PnP) Architects to join our diverse team at Arm! Our team focuses on PnP Analysis of Arm SoCs/SoPs (System-on-Package), System level infrastructure (SoC/SoP/Rackscale/Podscale) build together in pre- and post- silicon environments. Working closely with design teams and customers, we develop best-in-class silicon platforms across markets such as servers, accelerators, client, infrastructure, IoT, and automotive. Responsibilities: Efficiently drive and resolve architectural investigations and PnP tradeoff studies across various SoC (CPU, GPU, NPU, Media, IO, interconnects, memory controllers) and Platform components. Perform detailed workload characterization to identify performance bottlenecks and propose architectural solutions. Collaborate, coordinate, and drive consensus across architects, and IP teams. Conduct workload compaction to facilitate effective modeling. Create profiling and visualization frameworks to analyze with right level of abstraction. Contribute to automation for streamlining production processes Stay up-to-date on latest advancements in application development, workload characterization, and performance/power/thermal analysis Required Skills and Experience : Experience (+10 years) in SoC Performance Modeling and analysis in the semiconductor industry. A background in Electrical Engineering, Computer Engineering, or Computer Science with an expertise in computer architecture, and microarchitecture. Understanding of general-purpose CPU/GPU microarchitecture, including knowledge of areas such as processor pipelines, caches, and memory hierarchy. Proficient in C/C++ for programming for large-scale software development, familiarity with SystemC TLM, and Python scripting language skills. Excellent communication, and interpersonal skills with ability to convey effectively complicated solutions. Drive PnP analysis as an experienced SoC Performance and Power modeling Architect at Arm, focusing on diverse silicon platforms Nice To Have Skills and Experience : Knowledge of interconnect micro-architecture design, PCIe/CXL and CHI protocols. Understanding of workloads used for performance optimization under system constraints (TDP, Limits). Ability to work in a fast-paced environment with changing priorities and requirements Experience with Unix, scripting, and source control systems (e.g., Git, Subversion). In Return: We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding! Partner and customer focus Teamwork and communication Creativity and innovation Team and personal development Impact and influence Deliver on your promises Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arm s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm

Title: Sr Engineer - IT Applications (IBM Spectrum LSF (Load Sharing Facility)) About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Introduction We are seeking an experienced IT Engineer to join our team, responsible for supporting and optimizing our Design Engineering infrastructure. The ideal candidate will have the ability to troubleshoot and resolve complex technical issues related to tool infrastructure, IBM LSF, EDA license server management, and will be able to work collaboratively with cross-functional teams to ensure seamless tool integration and optimize design productivity. Your Job Install, configure, and maintain EDA and SW tools on GF servers Manage and optimize license configurations, to ensure efficient license utilization and server downtime Manage and optimize workloads using LSF, to ensure efficient CPU utilization and server minimize downtime Troubleshoot and resolve technical issues related to tool installation, configuration, and usage Develop and maintain documentation for EDA tool installation, configuration, and license usage Work with vendors to resolve technical issues, request new features, and stay up-to-date with the latest tool releases and updates Develop and implement automation scripts to improve tool efficiency and reduce manual errors Participate in the development and implementation of new design flows and methodologies Collaborate with IT teams to ensure EDA tool compatibility with existing infrastructure and future upgrades Required Qualifications : Bachelor s or Master s degree in Computer Science, Engineering, or a related field. 1-3 years of experience in IT architecture or systems engineering roles. 2-5 years Strong knowledge of IBM Load Sharing Facility 2-5 years Knowledge of Jenkins server, License server, Virtual machine configuration and maintenance. Proficiency in Linux and Windows operating systems Excellent communication and problem-solving skills, with the ability to work collaboratively with cross-functional teams Strong analytical and troubleshooting skills, with the ability to resolve complex technical issues Experience with scripting languages such as Python, Perl, or TCL Experience with Agile development methodologies and version control systems such as Git Preferred Qualifications: Experience with cloud-based EDA tool deployments and management Knowledge of containerization technologies such as Docker Experience with data analytics and visualization tools such as Tableau or Power BI Familiarity with DevOps practices and tools such as Jenkins, Ansible, or Puppet What We Offer: Competitive salary and benefits package Opportunity to work with a talented team of engineers and contribute to the development of innovative products Professional development and growth opportunities, including training and conference sponsorships Collaborative and dynamic work environment with a focus on teamwork and innovation. If youre a motivated and experienced EDA Engineer looking to join a dynamic team, please submit your resume for this role! GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency, and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations. Information about our benefits you can find here: https: / / gf.com / about-us / careers / opportunities-asia

Amazon Lab126 is an inventive research and development company that designs and engineers high-profile devices like the Kindle family of products. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc. Since then, we have worked to produce best-selling e-readers and tablets, as well as new inventions like Echo line of products, Fire TV and Fire phone. What will you help us create As a Signal Integrity Engineer, you will be part of Validation team that is exploring new hardware designs to improve our devices. In this role, you will be responsible for Signal Integrity aspects, compliance, and interoperability of package substrate, PCB, Cable solutions and system-level SI for interfaces like PCIe, DDR, Clocks etc. You will also be responsible for contributing to package and platform design guideline development. You will work closely with multi-disciplinary groups including Board Design, System Architects, IP developers, and Design Engineering, to verify and deliver complex, high volume SoCs that enable development of world-class hardware devices. In this role, you will be: Responsible for defining the design guidelines for internal and external design teams and delivering reference simulation docs for customers Performing modeling of package substrate/PCB channels elements in 3D/2D EM simulation tools. Working with silicon designers, platform designers, package designers, electrical validation teams, etc. to support interconnect and interface performance requirements. Reviewing and evaluating package and board design and providing review feedback. Responsible for providing power delivery solutions across platform, package and SOC level Definition of worst-case currents and voltage drop scenarios, MIM/decoupling allocation, grid choices and analysis, droop control, SOC ESD compliance, On-die droop detectors, usage of on-die delivery solutions like VR, LDO, and Power gates. Bachelors in Electrical or Computer Engineering/Computer Science 6+ years in working on validation of ASIC/SoC products High speed serial interface analog building blocks, protocol, specifications and test methods Familiarity with Simulation tools (ADS, HFSS, PowerSI, PowerDC, Hyperlynx) to execute SI-PI simulations is required. Experience with performing measurement, and correlating measurements to simulations. Experience with modeling and simulation of high-speed interface interconnects/channel. Excellent analytical and problem solving skills Masters in Electrical or Computer Engineering/Computer Science Understanding of Power & signal integrity concepts such as differential impedance, jitter, insertion loss, return loss, termination, etc. Scripting experience in any programming language (C++, Python, PERL, MATLAB) to develop automation scripts is a plus. Experience in Analog IP Characterization (SerDes, PLL, DDR) is desirable. Good understanding of High-Speed Analog/Digital Circuits, VLSI, semiconductor physics

Where Senior Analog Mixed-Signal Design Engineer Noida, Uttar Pradesh, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12261 Remote Eligible No Date Posted 23/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and experienced analog design engineer who thrives on tackling complex technical challenges and is eager to make a tangible impact on next-generation technology. You have an in-depth understanding of mixed-signal and analog circuit design, particularly in high-speed SERDES development. Your background in electrical, electronics, or VLSI engineering has equipped you with a strong foundation in CMOS device physics and nanometer technologies, and you are adept at applying this knowledge to develop innovative solutions. You enjoy collaborating with cross-functional teams, sharing your insights, and learning from peers across geographical boundaries. Your commitment to excellence drives you to ensure your designs not only meet but exceed standards for performance, power, and area optimization. You value clear communication and take pride in documenting your work, presenting your findings, and contributing to a culture of continuous improvement. Whether you are working independently or as part of a global team, you demonstrate initiative, adaptability, and a proactive approach to problem-solving. Your curiosity keeps you at the forefront of industry trends, and you are excited to work in an environment that encourages growth, mentorship, and technical leadership. Above all, you are motivated by the prospect of seeing your designs come to life in products that power the world s most advanced technologies. What You ll Be Doing: Designing and developing full-custom analog circuit macros, including analog front-end transceivers, voltage/current-mode drivers, delay-locked loops, phase-locked loops, regulators, equalizers (CTLE, FFE, DFE), impedance calibrators, serializers, deserializers, voltage-controlled oscillators, phase interpolators, bandgap references, and clock data recovery circuits for high-speed PHY IP in advanced CMOS technologies. Ensuring analog sub-block performance adheres to SerDes standards and architectural specifications, with a focus on achieving optimal power, area, and performance targets. Proposing and implementing design and verification strategies using advanced simulation tools to ensure high-quality, robust designs. Overseeing and collaborating on physical layout to minimize the effects of parasitics, device stress, and process variation. Presenting simulation data and design reviews to peers, customers, and cross-functional teams, and incorporating feedback. Documenting design features, test plans, and consulting on electrical characterization for SerDes IP products. Collaborating with diverse teams across different locations, contributing to a culture of technical excellence and innovation. The Impact You Will Have: Accelerate the development of high-performance silicon chips that power tomorrow s technologies enabling faster, more efficient data transfer in critical applications. Help Synopsys maintain its leadership in delivering industry-leading SERDES IP for a wide range of protocols (PCIe, Ethernet, SATA, USB, and more). Drive innovation in mixed-signal analog design, directly influencing the capabilities of next-generation SoCs and system solutions. Contribute to reducing customer project schedules by enabling robust, verified IP blocks that integrate seamlessly into customer designs. Enhance the quality, reliability, and performance of Synopsys IP offerings, strengthening our reputation and customer trust. Mentor and uplift peers, sharing knowledge and best practices to foster a high-performing, inclusive engineering culture. What You ll Need: Bachelor s (BE) with 3+ years or Master s (MTech) with 2+ years of relevant experience in mixed-signal/analog custom circuit design, with a degree in Electrical/Electronics/VLSI Engineering or closely related field. Strong expertise in CMOS circuit design fundamentals, device physics, and analog transistor-level circuit design in nanometer technologies. Hands-on experience with multi-Gbps high-speed design and familiarity with electrical specifications of protocols such as PCIe, Ethernet, SATA, and USB. Proficiency in EDA tools for SPICE simulation, static timing analysis (STA), and parasitic extraction, along with a solid understanding of sub-micron design methodologies. Experience in high-speed datapath full-custom design using digital/CMOS logic cells, including clock path optimization and timing verification. Familiarity with ESD/latch-up verification, mixed-signal analog design challenges, and understanding of crosstalk and coupling impacts on timing. Who You Are: Collaborative and open-minded, thriving in a diverse, global team environment. Analytical and detail-oriented, with a strong commitment to quality and continuous improvement. Effective communicator able to clearly document, present, and discuss complex technical concepts with clarity and confidence. Proactive problem-solver who takes initiative and adapts quickly to new challenges and evolving project requirements. Eager to learn, share knowledge, and mentor others within the team. Passionate about technology and motivated to contribute to industry-defining innovations. The Team You ll Be A Part Of: You will join our high-performing Analog Design SERDES team, a diverse group of engineers dedicated to developing cutting-edge high-speed analog circuits for SERDES IP. The team is known for its collaborative spirit, technical depth, and commitment to pushing the boundaries of what s possible in mixed-signal design. You ll work alongside experienced professionals both locally in Noida and across Synopsys global sites, sharing knowledge and driving innovation together. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Noida View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Where ASIC Digital Design, Staff Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12333 Remote Eligible No Date Posted 22/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and accomplished digital design engineer with an unyielding drive for excellence. You thrive in technically challenging environments, where your deep understanding of RTL design and system architecture allows you to craft innovative solutions for complex problems. With a solid foundation in electrical engineering or VLSI, you have accumulated over five years of hands-on experience in designing and implementing ASIC solutions, particularly focusing on high-performance protocols such as DDR, PCIe, USB, or HBM. Your expertise extends beyond individual contribution you are equally comfortable leading and mentoring small teams, fostering an environment of collaboration and shared learning. You are adept at translating functional specifications into detailed micro-architecture and design documents, always ensuring clarity and precision. Your technical toolkit includes mastery of Verilog/SystemVerilog, and you are well-versed in industry-standard flows encompassing linting, CDC analysis, synthesis, and static timing. You re not just a technical expert; you are a proactive communicator, an enthusiastic collaborator, and a natural problem solver who takes initiative and ownership of deliverables. Your ability to adapt to a global, multi-site team environment is matched only by your commitment to continuous learning and professional growth. If you re ready to take on a pivotal role in shaping next-generation silicon IP, Synopsys is where your aspirations and impact can soar. What You ll Be Doing: Architecting, designing, and implementing state-of-the-art RTL for the next-generation high-performance DDR PHY and related IP cores. Translating standard and functional specifications into detailed architecture, micro-architecture, and design documentation for medium- to high-complexity features. Contributing as an individual designer handling RTL coding, lint/CDC analysis, synthesis, debug, and test plan development. Collaborating with global teams across multiple sites, ensuring cohesive project execution and knowledge sharing. Leading or mentoring small teams of designers, providing technical guidance and fostering professional development. Engaging in continuous process improvement, proposing and implementing enhancements to design flows and methodologies. Troubleshooting and resolving design and verification issues, ensuring robust and high-quality deliverables. The Impact You Will Have: Directly contributing to the design and delivery of high-performance IP cores that power industry-leading semiconductor solutions worldwide. Elevating Synopsys reputation for technical excellence and innovation in the IP design space. Accelerating the adoption of advanced protocols and interfaces in cutting-edge technologies. Enabling customers to achieve faster time-to-market and superior silicon performance. Mentoring and uplifting team members, fostering a culture of knowledge sharing and technical growth. Driving continuous improvement in design methodologies, enhancing efficiency and product quality. Supporting Synopsys mission to remain at the forefront of the Era of Pervasive Intelligence through breakthrough silicon solutions. What You ll Need: Bachelor s or Master s degree in Electrical Engineering, Electronics, VLSI, or related discipline. 5+ years of relevant industry experience in ASIC digital design, with a focus on protocols like DDR, PCIe, USB, or HBM. In-depth experience with RTL coding in Verilog/SystemVerilog and simulation tools for ASIC design. Strong command of design flows, including lint, CDC, synthesis, static timing analysis, and formal verification. Hands-on expertise in architecting and implementing control path-oriented designs (e.g., asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces). Familiarity with scripting languages such as Perl or Shell an advantage. Demonstrated ability to technically lead or mentor small teams of engineers. Who You Are: A collaborative team player who thrives in a multi-site, multicultural environment. An effective communicator, able to translate complex technical concepts for diverse audiences. A proactive problem-solver with strong analytical and troubleshooting skills. Self-motivated, showing high initiative and ownership of responsibilities. Adaptable and eager to learn, always seeking opportunities for personal and professional growth. Committed to fostering a positive, inclusive, and innovative team culture. The Team You ll Be A Part Of: You will join the R&D Solutions Group at our Bengaluru Design Center, a dynamic and diverse team dedicated to the design and development of industry-leading DesignWare IP cores. As a Technical Individual Contributor, you will collaborate with global experts in a multi-site environment, contributing to technically challenging projects that push the boundaries of silicon design. The team values innovation, continuous learning, and the sharing of knowledge, offering ample opportunities for growth and leadership. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Where Analog Circuit Design Specialist Noida, Uttar Pradesh, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12346 Remote Eligible No Date Posted 22/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. Our Silicon Design & Verification business leads the industry in enabling customers to design and verify advanced silicon chips faster and with more reliability. We develop the next-generation processes and models that optimize chips for power, cost, and performance, shaving months off project schedules for our global clientele. We believe in fostering an inclusive and diverse environment where every voice is valued and innovation thrives. You Are: You are a passionate and experienced Analog/Mixed-Signal (A&MS) Circuit Design Engineer with a track record of excellence in high-speed physical interface development. With a deep foundation in CMOS circuit design, device physics, and nanometer technologies, you thrive on solving complex challenges at the intersection of analog and digital domains. You are energized by working on industry-leading projects and are adept at architecting, designing, and validating advanced circuits such as transmitters, receivers, clocking circuits, equalizers, serializers, de-serializers, and analog front ends. Your expertise allows you to optimize for performance, area, and power, and you are comfortable with layout considerations and parasitic optimizations. You value diversity and inclusion, recognizing the strength that comes from varied perspectives and backgrounds. You are ready to contribute to a culture of innovation, respect, and excellence helping Synopsys remain at the forefront of the smart everything revolution. What You ll Be Doing: Designing and developing high-speed analog and mixed-signal full-custom circuit macros, including transmitters, receivers, clocking circuits, equalizers, serializers, de-serializers, and analog front ends for PHY IPs in advanced CMOS technologies (planar and finFET). Analyzing and implementing various analog circuit techniques to optimize dynamic/static power, enhance performance, and reduce silicon area. Collaborating with global teams to define micro-architectures from specifications and create robust simulation environments for design verification. Performing transistor-level circuit design, simulation, and troubleshooting in nanometer processes, with a focus on reliability and manufacturability. Working closely with layout engineers to optimize parasitics, ensure design closure, and address layout-dependent effects. Participating in design reviews, providing technical guidance, and mentoring junior engineers within a high-performing, diverse team. Adopting and developing automation and scripting to streamline design and verification flows, leveraging languages such as Verilog-A and others as needed. The Impact You Will Have: Advance the state-of-the-art in high-speed PHY IP development, contributing directly to next-generation technology in AI, IoT, 5G, and automotive industries. Enable Synopsys customers to achieve faster time-to-market with optimized, reliable, and high-performance silicon solutions. Drive innovation in low-power and high-speed circuit design, helping customers meet stringent power and area targets. Enhance Synopsys reputation as a global leader in silicon design and verification through technical excellence and customer success. Mentor and elevate the skills of team members, fostering a collaborative and growth-oriented culture. Contribute to a diverse and inclusive workplace, ensuring a wide range of perspectives and ideas inform our solutions. What You ll Need: BE + 5 years or MTech + 4 years of relevant experience in Electrical/Electronics/VLSI Engineering or closely related field. Strong fundamentals in CMOS circuit design, device physics, and sub-micron/nanometer methodologies. Hands-on experience in analog transistor-level circuit design for high-speed applications (Multi-Gbps, PAM4 SERDES architectures). Proficiency in SPICE simulations, reliability analysis, and optimizing for layout parasitics. Ability to micro-architect circuits from specifications, set up verification environments, and debug complex analog/mixed-signal circuits. Basic proficiency with automation/scripting languages and familiarity with Verilog-A is a plus. Experience collaborating with cross-site, multicultural teams and strong documentation skills. Who You Are: Innovative thinker with a problem-solving mindset and a passion for continuous learning. Collaborative team player who values diversity, inclusion, and open communication. Detail-oriented, quality-focused, and committed to delivering results on time. Strong interpersonal and mentoring skills, able to guide and support less experienced team members. Adaptable and resilient, comfortable working in a fast-paced, dynamic environment. The Team You ll Be A Part Of: You will join a dynamic, high-performing team dedicated to the design and development of high-speed physical interfaces for advanced semiconductor products. Our team is composed of talented engineers with deep expertise in analog and mixed-signal design, working collaboratively across multiple sites worldwide. We value innovation, knowledge-sharing, and a culture of mutual respect, enabling every team member to grow and contribute to industry-leading solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Noida View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!