Design and develop analog/mixed-signal blocks for PCIe 6 and PCIe 7 PHY designs. Ensure designs meet PCIe protocol standards, optimizing for performance, power, and area targets. Support the porting of PHY designs to different technology nodes, maintaining signal integrity and performance. Collaborate with cross-functional teams to integrate analog circuits into larger SerDes PHY systems. Implement verification strategies for high-speed analog/mixed-signal circuits using advanced simulation tools. Work closely with physical layout teams to minimize parasitics, device stress, and process variation impacts. Analyze simulation and measurement data for design validation and compliance with PCIe standards. Provide technical guidance to junior engineers in analog/mixed-signal design methods. Document design features, specifications, and test plans for future reference. Work with the characterization team to validate the electrical performance of circuits in silicon. The Impact You Will Have: Drive the development of cutting-edge PCIe 6 and PCIe 7 PHY designs, pushing the boundaries of high-speed analog and mixed-signal circuits. Ensure that Synopsys designs meet the highest standards of performance, power efficiency, and area optimization. Enhance the reliability and integrity of our analog circuits as they are ported to new technology nodes. Foster innovation through collaboration with diverse teams, integrating leading-edge analog circuits into sophisticated SerDes PHY systems. Contribute to the verification and validation of high-speed circuits, ensuring compliance with stringent PCIe standards. Mentor and guide junior engineers, nurturing the next generation of top-tier analog designers. What You ll Need: PhD with 3+ years, or MTech/MS with 8+ years of experience in analog/mixed-signal circuit design, with experience in high-speed interfaces such as PCIe or SerDes PHY designs. Strong experience in transistor-level design of high-speed analog building blocks, such as LDOs, Bandgap references, ADC/DAC, PLLs, DLLs. Experience in high-speed SerDes AFE (Analog Front-End) development, including CTLE and CDR design. Experience designing high-speed SerDes transmitters, with knowledge of equalization techniques (e.g., DFE, FIR filters, TX pre-emphasis). Understanding of jitter budgeting analysis, including sources of jitter and strategies for minimizing its impact. Strong knowledge of CMOS technologies, including finFET and GAA processes. Good understanding of the PCIe protocol, signal integrity requirements, and high-speed clocking. Ability to provide input on layout design to minimize the effects of parasitics and process variations. Who You Are: Detail-oriented with a passion for innovation and excellence. Proactive and able to work independently with limited supervision. Strong communicator capable of effectively collaborating with cross-functional teams. Mentor and leader, eager to share knowledge and help develop junior engineers. Results-driven with a focus on delivering high-quality, reliable designs

An Emulation Expert with deep knowledge of IP interfaces such as PCIe and DDR, and experience with Zebu. You have a proven track record in IP product development focused on emulation and verification. You thrive in a matrixed, international, and team-oriented environment with multiple stakeholders. Your hands-on approach, collaborative mindset, and proactive attitude drive results. You are passionate about right-first-time development, ensuring traceability of all verification requirements and covering the entire ecosystem of Controller and PHY. What You ll Be Doing: Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification of all its functions, covering both the Controller and PHY. Reporting metrics and driving improvements in Emulation IP. Using your expertise to drive requirements for the Emulation IP and ensure its correct usage and deployment in verification strategies for both Controller and PHY. Staying ahead of evolving standards, understanding future changes, ECNs, and specification errata, and driving this understanding into both the Emulation IP and Design IP teams. Reviewing test plans in both Emulation IP and Design IP to ensure they deliver the required function, feature, and quality to be best in class. The Impact You Will Have: Enhancing cross-functional collaboration to improve product quality and end customer satisfaction. Changing the mindset in the way we use Emulation IP in validating digital designs and architectures. Driving innovation in defining requirements for IP product development, in the context of Emulation. Evolving and integrating best-in-class methodologies within the organization. Standardizing and optimizing workflows to increase efficiency and compliance. What You ll Need: 8+ years of relevant experience. Results-driven mindset. Subject Matter Expert in PCIe and DDR interfaces. Experience with Zebu in the context of technology and IP verification . Proven track record in IP product development, specifically emulation . Experience in cross-functional collaborations. Excellent communication skills and a beacon for change. Adaptability and comfort in a matrixed, international environment .

Developing SignOff ECO optimization algorithms and heuristics. Debugging issues related to design loading and timing/power optimization. Striving for continuous improvements in QoR to achieve faster timing convergence with optimal power overhead. Collaborating with a team of engineers to develop technical solutions to complex problems. Communicating with product engineers to understand and define problem scope. Ensuring strict performance and quality requirements are met. The Impact You Will Have: Enhancing the performance and efficiency of PrimeClosure, the industrys first AI-driven signoff ECO solution. Contributing to the development of cutting-edge algorithms that optimize timing and power in chip design. Improving the overall quality and reliability of our products through rigorous debugging and testing. Driving innovation and continuous improvement in our engineering processes. Supporting customer success by resolving issues and implementing new features based on their feedback. Helping shape the future of AI-driven optimization in the semiconductor industry. What You ll Need: A degree in Computer Science or Electronics. 5+ years of experience in relevant field Strong analytical and problem-solving skills. Proficiency in C/C++ and Linux. Excellent communication and teamwork abilities. A passion for technology and innovation. Who You Are: A collaborative team player who thrives in a dynamic and innovative environment. A proactive and self-motivated individual with a strong attention to detail. An excellent communicator who can articulate complex ideas clearly and effectively. A creative thinker who is always looking for new ways to solve problems and improve processes. A dedicated professional committed to delivering high-quality work

You are a highly skilled and motivated GenAI/LLM Researcher/Engineer with a passion for pioneering advancements in the field of General Artificial Intelligence and Large Language Models. With a strong foundation in AI/ML and software development, you are adept at leveraging your expertise to revolutionize the Electronic Design Automation (EDA) domain. Your in-depth understanding of UVM and EDA tools is complemented by your ability to collaborate effectively with cross-functional teams. You thrive in a dynamic environment, where your innovative mindset and problem-solving abilities drive the development of cutting-edge solutions. Your proactive approach to staying updated with industry trends and advancements ensures that you remain at the forefront of AI technology. What You ll Be Doing: Research and develop novel GenAI/LLM-based solutions for EDA applications, such as Design automation, Verification, and Optimization. Focus on UVM automation using GenAI techniques. Collaborate with cross-functional teams to integrate GenAI/LLM technologies into existing EDA tools and workflows. Design, implement, and optimize AI models using popular frameworks (e.g., TensorFlow, PyTorch). Develop software applications and tools to demonstrate GenAI/LLM capabilities in EDA. Publish research papers and present at conferences to showcase innovative solutions. Stay up-to-date with industry trends and advancements in GenAI/LLM. Work closely with customers to understand their needs and provide tailored solutions. Participate in agile development methodologies, ensuring timely delivery of high-quality solutions. The Impact You Will Have: Drive innovation in the EDA domain through the application of cutting-edge GenAI/LLM technologies. Enhance the efficiency and accuracy of design automation and verification processes. Contribute to the development of state-of-the-art AI models that set new industry standards. Facilitate the integration of advanced AI solutions into existing workflows, improving overall productivity. Shape the future of EDA by introducing novel, AI-driven methodologies. Establish Synopsys as a leader in the application of GenAI/LLM in the semiconductor industry. What You ll Need: Bachelors/Masters in Computer Science, Electrical Engineering, or related field. 5+ years of experience in AI/ML research and development. Strong programming skills in Python, C++, or Java. Experience with popular AI/ML frameworks (e.g., TensorFlow, PyTorch). Familiarity with EDA tools and workflows, and prior experience in UVM. Excellent problem-solving skills and analytical thinking

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: Strong desire to learn and explore new technologies. Demonstrates good analysis and problem-solving skills. Prior knowledge and experience in tools like DC, ICC2, PT-SI,FC is a definite advantage. Should be a strong team player, excellent communicator as the role involves daily technical interaction with local, US counter parts. What You ll Be Doing: He/She will be part of SNPS DDR/HBM/Ucie IP implementation team and responsible for the implementation and integration of world class DDRs at the cutting-edge technology nodes. Timing closure above ~4GHz, mixed signal had macro IP integration, Building the efficient clock trees with very tight skew balancing are some of the challenges as part of day-to-day job. Prior working knowledge in the DDR/HBM/HBI timing closure, implementation would be an added advantage. Should be very hands-on and able to technically lead a team of 4-6 junior engineers towards successful completion of project on-time and with top quality. Who You Are: Typically requires a minimum of 6+ years of related experience after the post graduation. Possesses a full understanding of specialization area plus working knowledge of multiple related areas. A team player Independently resolves a wide range of issues in creative ways on a regular basis. Customarily exercises independent judgment in selecting methods and techniques to obtain solutions. Performs in project leadership role. Contributes to complex aspects of a project. Determines and develops approach to solutions. Work is independent and collaborative in nature. Provides regular updates to manager on project status. Represents the organization on business unit and/or company-wide projects. Guides more junior peers with aspects of their job.

Implementing and power signoff of world-class DDRs at cutting-edge technology nodes. Achieving timing closure above ~2GHz and integrating mixed signal macro IPs. Building efficient clock trees with very tight skew balancing. Providing regular updates to your manager on project status. Guiding junior peers with aspects of their job and contributing to their development. Representing the organization on business unit and/or company-wide projects. The Impact You Will Have: Driving the implementation of cutting-edge DDR technology, contributing to the advancement of high-performance computing. Ensuring the power efficiency and performance of our silicon chips, crucial for our competitive edge. Enhancing the reliability and integration of mixed signal macro IPs. Contributing to the overall success and innovation of Synopsys IP solutions. Mentoring junior engineers, fostering a culture of continuous learning and improvement. Representing Synopsys in key projects, influencing the direction and success of our initiatives. What You ll Need: Minimum of 5+ years of related experience in ASIC Physical Design. Proficiency in tools like DC, ICC2, StarRC, and PT-SI. Strong understanding of timing closure, power signoff, and mixed signal macro IP integration. Experience with DDR power signoff and clock tree building. Excellent problem-solving and analytical skills. Who You Are: A strong team player with excellent communication skills. Independent and collaborative, capable of working with minimal supervision. Creative and innovative, able to develop unique solutions to complex problems. Detail-oriented and organized, ensuring high-quality project outcomes. Passionate about continuous learning and professional growth.

Floor planning, power planning, placement, and optimization Clock tree building and optimization Routing and optimization Timing constraints closure, synthesis, and formal verification Extraction, IR drop analysis, EM analysis, and signal integrity Physical verification and flow development for advanced technology nodes The Impact You Will Have: Enhance the best practices of the physical design flow Contribute to the successful implementation of high-performance digital designs Drive innovations in low-power design and high-speed clock distribution Ensure the integrity and reliability of complex IC designs Support the development of cutting-edge technology that shapes the future Collaborate with cross-functional teams to meet customer requirements What You ll Need: Solid engineering understanding of IC design concepts Strong knowledge of the full design cycle from RTL to GDSII Expertise in implementation flows and methodologies for deep sub-micron designs Experience in high-performance digital design, CAD, high-speed design, low-power design, and high-speed clock design and distribution Proven experience with project tape-outs and timing closure Proficiency in software and scripting skills (Perl, Tcl, Python) Knowledge of Synopsys tools, flows, and methodologies

At minimum, a Bachelor s degree in engineering is required with 12+ years of digital design experience using Verilog. Strong background in RISC architectures required. Working experience in RISC microprocessor IP design, programming at assembly and C/C++ level, DSP skills, an understanding of multi-core architectures and development techniques are a plus. Experience with multi-site development is helpful. The successful candidate is expected to: Design embedded RISC microprocessor IP at architectural and RTL level Write High-level architecture and micro-architecture specifications of the design Optimize design for performance, speed, area and power, generate hardware benchmarks and analyze results Develop standalone Verilog testbenches to verify their module Debug design issues / bugs working closely with the verification team Maintain our current processor product line and their derivative products Develop and maintain project plans. Work closely with program managers Good written, oral and problem-solving skills desired along with good communication skills and inter-person skills Work with multi-site, multi-time zone, multi-cultural teams on various aspects of the product like design, implementation, physical design, verification

You are a seasoned professional with a passion for analog design and a knack for solving complex problems With a strong foundation in CMOS processes and deep submicron technologies, you bring a wealth of knowledge and experience to the table You thrive in a collaborative environment, where your excellent communication skills enable seamless interactions with internal development teams You are adept at executing circuit design tasks with precision, ensuring the highest product quality and efficiency Your familiarity with ASIC design flow and JEDEC standards for DDR interfaces sets you apart, and you are always eager to learn and adapt to new challenges Your technical acumen, combined with your dedication and innovative mindset, makes you an ideal fit for our team What You ll Be Doing: - Ownership of complete physical implementation at block level & chip level. Responsible for delivering timing clean blocks/chip level that meet design targets. - DRC, LVS & IR closure. Evaluates all aspects of the physical design flow from place and route, timing, PV & IR and is able to setup these flows. - Experience in all chip level tasks (P&R, STA, PV, IR) . Work closely with the frontend design team to resolve design issues . The Impact You Will Have: * Enhancing the performance and efficiency of our silicon IP portfolio. * Contributing to the rapid integration of advanced capabilities into SoCs. * Reducing the time-to-market and risk for our customers products. * Driving innovation in analog design and setting new industry standards. * Strengthening Synopsys position as a leader in chip design and verification. * Empowering the development of high-performance, differentiated products. What You ll Need: - Candidates with MSEE/BSEE with 5+ years of related experience. Possesses in depth understanding of specialization area plus working knowledge of one other related area. - Resolves issues in creative ways. - Exercises judgement in selecting methods and techniques to obtain solutions. - Executes project responsibilities from start to completion. - Contributes to moderately complex aspects of a project. - Determines and develops recommendations to solutions. - Works on team-driven or task-oriented projects. - May guide more junior peers with aspects of their job. - Networks with senior internal and external personnel in own area of expertise. - Strong knowledge on scripting using tcl, perl . Who You Are: * A collaborative team player with a proactive approach. * Detail-oriented with a commitment to quality and efficiency. * Innovative and adaptable, always seeking to learn and grow. * Effective communicator, able to convey technical information clearly. * Problem-solver with strong analytical skills.

As an ideal candidate, you are a passionate and highly skilled engineer with a keen interest in ASIC physical design. You possess a strong foundation in electronics engineering or computer science, ideally with a Bachelors degree and a minimum of 3 years of related experience. You have a methodical approach to problem-solving and are proficient in scripting languages like Unix, Perl, and TCL. Your exposure to Verilog/VHDL and understanding of microprocessor design make you a valuable asset to any team. You are a team player with excellent written and verbal communication skills, capable of working in a collaborative international environment. Your enthusiasm for learning and applying new technologies drives you to continuously improve and contribute to cutting-edge projects. What You ll Be Doing: Contributing to the physical design and implementation of our highly optimized hardware IP for the ARC family of configurable processors. Working on the full SOC design cycle with a focus on physical design tasks, including floorplanning, placement, routing, and timing closure. Collaborating with cross-functional teams to ensure the successful integration and verification of our microprocessor IP. Assisting in customer sales and design-ins of our IP by providing technical support and expertise. Participating in in-house test chip designs and development platforms to explore potential applications of our microprocessor IP. Engaging in benchmarking and qualification activities to ensure the highest performance and reliability of our products. The Impact You Will Have: Enhancing the performance and efficiency of our microprocessor IP through innovative physical design techniques. Contributing to the development of state-of-the-art embedded designs used in various high-tech applications. Supporting the successful deployment of our IP in customer projects, leading to high customer satisfaction and repeat business. Driving continuous improvement in our implementation flows and methodologies. Helping Synopsys maintain its leadership position in the semiconductor industry by delivering top-quality products. Fostering a collaborative and innovative work environment by sharing your expertise and learning from others. What You ll Need: Bachelor s degree in electronics engineering or computer science; a Master s degree is a plus. Minimum of 3 years of related experience in ASIC physical design. Proficiency in Unix, Perl, and TCL scripting. Exposure to Verilog/VHDL and understanding of microprocessor design. Strong written, verbal, and methodical skills. Who You Are: A collaborative team player with excellent communication skills. A methodical problem-solver with a keen attention to detail. Enthusiastic about learning and applying new technologies. Adaptable and able to work in an international, multi-disciplinary team. Dedicated to continuous improvement and innovation.

Implementing DDR and HBM PHYs for customer ASICs and SOCs in the DDR and HBM PHY Hardening service line. Performing synthesis, physical design, verification, design for test, and ATPG. Contributing as a senior member of a design team or as a project design engineer working with both internal and external design teams. Providing regular updates to the manager on project status. Representing the organization on business unit and/or company-wide projects. Guiding more junior peers with aspects of their job and frequently networking with senior internal and external personnel in your area of expertise. The Impact You Will Have: Enhancing the reliability and performance of DDR and HBM PHYs for customer ASICs and SOCs. Contributing to the success of complex projects through innovative problem-solving and technical expertise. Ensuring timely delivery of high-quality design solutions to our customers. Improving the efficiency and effectiveness of the design process through your autonomous judgment and technical knowledge. Strengthening Synopsys position as a leader in chip design and verification through your contributions. Mentoring and guiding junior team members, fostering a collaborative and innovative team environment. What You ll Need: A minimum of 5+ years of related experience in ASIC Physical Design. Proficiency in state-of-the-art CAD tools such as DC, PT, ICC2/FC, and ICV. Experience with advanced technologies like FinFet. Strong problem-solving skills and the ability to autonomously resolve a wide range of issues. Excellent verbal and written communication skills. Who You Are: An innovative thinker with a passion for technology and continuous learning. A collaborative team player who excels in a dynamic and fast-paced environment. A mentor and guide for junior team members. A strong communicator with the ability to network effectively with senior personnel. A composed and reliable professional who can handle risks and uncertainty with ease.

As an ideal candidate, you are a seasoned professional with a passion for innovation and a deep understanding of ASIC design and verification. You have a proven track record in developing high-level verification environments using System Verilog/UVM and possess a keen eye for detail. Your expertise in memory interface protocols like DDR and LPDDR sets you apart, and you excel in debugging and problem-solving skills. You are self-motivated and possess excellent communication skills, enabling you to work seamlessly within global teams. Your leadership abilities allow you to guide technical teams and enhance verification strategies and test environments, ensuring high-quality deliverables. What You ll Be Doing: Specify, design, and implement state-of-the-art verification environments for the DesignWare family of synthesizable cores. Perform verification tasks for IP cores, working closely with RTL designers. Drive ownership of critical areas of verification along with a team of talented verification engineers. Manage and own a team to develop and implement advanced test plans and test environments at both unit and system levels. Code and debug test cases, implementing complex checkers and assertions. Extract and review functional coverage (FC) and code coverage metrics, ensuring quality metric goals are met. Manage regressions and contribute to the continuous improvement of verification strategies and test environments. The Impact You Will Have: Enhance the quality and efficiency of our verification processes, ensuring robust and reliable IP cores. Contribute to the development of cutting-edge technologies that power the Era of Smart Everything. Enable the creation of high-performance silicon chips and software content, driving innovation in various industries. Collaborate with a global team of experienced verification engineers, fostering a culture of knowledge sharing and continuous learning. Play a key role in the success of Synopsys DesignWare IP Verification R&D team, contributing to our leadership in chip design and software security. What You ll Need: BS/MS in Electrical Engineering or Electronics and Communication Engineering with 10+ years of relevant experience. Proven experience in developing HVL (System Verilog/UVM) based test environments. Expertise in developing and implementing test plans, checkers, and assertions. Proficiency in extracting verification metrics such as functional coverage and code coverage. Experience with memory interface protocols (DDR, LPDDR) and IP design and verification processes

Hands-on experience of implementing digital block using state of the art gate to GDSII ASIC flows mainly including Design Initialization, Power planning, Floor planning/Macro placement, Scan-chain reordering, CTS, Route and chip finishing steps Perform Physical Implementation of blocks starting from gate netlist till gds out Perform signoff verifications including Layout verifications (DRC, LVS, Antenna) and Reliability verifications (EMIR, ESD) of the implemented blocks Ownership of writing MCMM and UPF for the block designs Provide handoff data to other signoff closure like STA, Formality, Layout and Reliability verification Job Requirements In-depth understanding of the ASIC Physical design flow steps of starting from Gate netlist Experience in Testchip implementation and testing exposure is a plus Exposure to Synopsys Tool set (such as FC/ICC2, Primetime, Formality, ICV) is highly desirable Exposure to FinFET designs is desirable Experience in working on IO integration with Wire-bond or Flip-chip design would be big plus Experience : Min 5 years of Relevant Physical design domain Education : B.E/B.Tech/M.Tech in ECE/EE

As Staff Application Engineer (AE) , you will be Working on latest Synopsys implementation technologies ( Machine Learning , Physical Synthesis , Multi Source CTS etc ) to solve complex PPA challenges faced by Synopsys customers. Working on benchmarks to displace competition implementation solutions Working with customers to develop and debug RTL-GDS implementation methodologies and flows. Providing technical solutions by identifying the design and/or EDA tool issues and provide appropriate solution for customers Effectively translate the findings into requirements for R&D to improve both tool behaviour with enhancements as adaptive long-term solutions. Involved in deployment of new technologies on latest EDA versions and enable customers to migrate to newer versions achieving best PPA. Coming up with proactive understanding of customers pain point and come up with innovative solutions to address the same. Closely interacting with Synopsys R&D team and product development team to develop future technologies This role requires you to act as customers advocate while talking to inhouse R&D and be a product brand ambassador while engaging with customers. Requirements At-least 5 years of experience in Physical Implementation RTL-GDS. Experience in unsupervised debugging and resolving synth & PnR implementation challenges. Candidate must have good exposure towards methodology changes to achieve targeted PPA metrics for complex designs. Proficiency in Synopsys implementation tools is an advantage The person must be self-motivated and dedicated with solid debug skills. Requires proficiency in scripting (tcl / Unix / Perl / Python). Excellent communication skills including ability to interface with customers and business unit personnel are essential. Who You Are: * Proactive and solution-orien ted with a strong problem-solvin g mindset. * Excellent communicator, able to convey technical information clearly and effectively. * Collaborative team player with strong interpersonal skills. * Adaptable and able to thrive in a fast-paced, dynamic environment. * Committed to continuous learning and professional development.

Our Silicon IP business is all about integrating more capabilities into an SoC faster. We offer the world s broadest portfolio of silicon IP predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk. Responsibilities: DDR I/O Circuit design Requirements- Qualification: BTech/MTech Skills/Experience: MTech+3years / BTech+5years Knowledge of CMOS processes and issues in deep submicron process technologies. CMOS circuit design and layout methodology & flow; basic understanding of analog/mixed signal circuitry, familiarity with basic ESD concepts is an advantage. Familiarity with ASIC design flow. Knowledge of JEDEC requirements for DDR interfaces & standards, DDR Timing, ODT and SDRAM functionality would be a plus. Ability to execute assigned circuit design tasks with best product quality and efficiency. Good written and verbal communication skills in interactions with internal development teams.

Working on benchmarks to displace competition implementation solutions. Working on developing and debugging RTL-GDS implementation methodologies and flows. Providing technical solutions by identifying the design and/or EDA tool issues and provide an appropriate solution for customers. Effectively translate the findings into requirements for R&D to improve both tool behavior with enhancements as adaptive long-term solutions. Involved in deployment of new technologies on latest EDA versions and enable customers to migrate to newer versions achieving best PPA. Coming up with a proactive understanding of customers pain point and coming up with innovative solutions to address the same. Closely interacting with Synopsys R&D team and product development team to develop future technologies. This role requires you to act as customers advocate while talking to inhouse R&D and be a product brand ambassador while engaging with customers. The candidate must have good exposure to methodology changes to achieve targeted PPA metrics for complex designs. At least 5 years of experience in Physical Implementation RTL-GDS. Experience in autonomously debugging and resolving synth & PnR implementation challenges. Proficiency in Synopsys implementation tools is an advantage. The individual must be self-motivated and dedicated with strong debugging skills. Requires proficiency in scripting (tcl / unix / perl). Excellent communication skills including the ability to interface with customers and business unit personnel are essential.

Application Engineering : Staff Engineer , you will be Working on latest Synopsys implementation technologies ( Machine Learning , Synthesis, Physical Synthesis , Multi Source CTS etc ) to solve complex PPA challenges faced by Synopsys customers Working on benchmarks to displace competition implementation solutions Working on developing and debugging RTL-GDS implementation methodologies and flows by collaborating with key stake holders Providing technical solutions by identifying the design and/or EDA tool issues and provide appropriate solution for customers Effectively translate the findings into requirements for R&D to improve both tool behaviour with enhancements as adaptive long-term solutions. Involved in deployment of new technologies on latest EDA versions and enable customers to migrate to newer versions achieving best PPA Coming up with proactive understanding of customers pain point and come up with innovative solutions to address the same. Closely interacting with Synopsys R&D team and product development team to develop future technologies This role requires you to act as customers advocate while talking to inhouse R& D, and be a product brand ambassador while engaging with customers. Requirements At-least 5+ years of experience in Physical Implementation RTL-GDS. Experience in independently debugging and resolving Synth & PnR implementation challenges. Ability to handle complete project independently through timely successful outcome.. Candidate must have good exposure towards methodology changes to achieve targeted PPA metrics for complex designs. Proficiency in Synopsys implementation tools is an advantage The individual must be self-motivated and dedicated with strong debug skills Requires proficiency in scripting ( tcl / unix / perl ) Excellent communication skills including ability to interface with customers and business unit personnel are essential.

Designing and verifying complex Analog Mixed-Signal layouts, ensuring high-quality and reliable IPs. Collaborating with cross-functional teams to optimize layout designs for performance and manufacturability. Utilizing advanced tools and methodologies to mitigate deep submicron effects. Conducting floor-planning, routing, and top-level verification. Ensuring compliance with DRC, LVS, LPE standards and addressing ESD and latch-up considerations. Optimizing power routes and addressing EM and IR considerations for robust designs. The Impact You Will Have: Enhancing the performance and reliability of our high-speed SerDes IPs and other critical components. Driving innovation in Analog Mixed-Signal layout design, contributing to cutting-edge technology developments. Ensuring seamless integration and functionality of our IPs in diverse applications. Improving design efficiency and manufacturability through advanced layout techniques. Contributing to the success of our product development lifecycle by delivering high-quality designs. Supporting our mission to lead in chip design and IP integration, shaping the future of technology. What You ll Need: 6+ years of experience in Analog Mixed-Signal layout and verification. Advanced understanding of deep submicron effects and mitigation techniques. Proficiency in using advanced layout design tools and methodologies. Solid understanding of CMOS and FinFET layouts and process technology in 28nm and below. Familiarity with layout design flow, including top-level verification flow, DRC/LVS, LPE.

You are a seasoned professional with a strong background in Custom Analog Design, possessing over 5 years of experience in the field. You have a deep understanding of analog circuit building blocks such as amplifiers, reference circuits, and clock generators. Your expertise extends to working closely with design and CAD teams to develop and deploy simulation methodologies that enhance design verification efficiency. You are adept at using industry-standard design verification and simulation tools like HSPICE, Primesim, and VCS. Additionally, you have a knack for scripting and automation using tools such as Perl, Python, and TCL. You are passionate about providing support and training to your peers, fostering a collaborative and innovative environment. What You ll Be Doing: Designing, developing, modifying, and evaluating physical IP such as SERDES, DDR, and Memory. Collaborating with design and CAD teams to develop and deploy simulation methodologies. Using existing tools and scripting skills to automate design and simulation flows/tasks. Providing support and training to enhance team capabilities. Analyzing and optimizing analog circuit building blocks like amplifiers, reference circuits, and clock generators. Ensuring efficient use of tools to improve design verification time. The Impact You Will Have: Enhancing the efficiency and accuracy of analog design verification processes. Contributing to the development of high-performance silicon chips and software content. Driving innovation in analog circuit design and simulation methodologies. Improving the overall design and development cycle within the team. Providing valuable training and support to team members, fostering a collaborative environment. Playing a key role in the success of Synopsys technology and product offerings. What You ll Need: BE/MTech in Electronics or a related field. 5+ years of experience in Custom Analog Design. Proficiency in industry-standard design verification and simulation tools (HSPICE, Primesim, VCS). Strong scripting skills using Perl, Python, and TCL. In-depth knowledge of analog circuit building blocks like amplifiers, reference circuits, and clock generators. Who You Are: A collaborative team player with excellent communication skills. A problem solver with a keen eye for detail and a passion for innovation. A proactive learner who stays updated with the latest industry trends and technologies. A mentor who enjoys sharing knowledge and helping others grow. An analytical thinker who can evaluate complex problems and develop effective solutions.

Supporting development and verification of ASIC digital designs for next-generation NRZ and PAM-based SerDes products. Setting up and running lint/cdc/rdc checks using VC-Spyglass and synthesis flow using Design Compiler/Fusion Compiler. Working with Verilog and VCS to ensure design accuracy. Defining synthesis design constraints and resolving STA issues. Setting up and running FPGA prototyping flows to map RTL designs to Xilinx FPGAs. The Impact You Will Have: Contributing to the development of cutting-edge SerDes products that lead the industry. Enhancing the performance, power, and size efficiency of our silicon IP offerings. Enabling rapid market entry for differentiated products with reduced risk. Driving innovation in high-speed digital design and data recovery circuits. Supporting the creation of high-performance silicon chips and software content. Collaborating with a world-class team to solve complex design challenges. What You ll Need: BSEE or MSEE with a minimum of 2 years of experience in digital design and front-end flows. Proficiency in running lint/cdc/rdc checks and synthesis flow. Experience in coding, verifying Verilog and System Verilog design. Experience of working with minimum supervision and owning and delivering for front-end activities in IP/SOC. Experience of leading technically for front-end activities. Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows. Scripting experience in Shell, Perl, Python, and TCL (preferred). Who You Are: Excellent communicator with the ability to interact with diverse teams. Self-motivated and proactive, with a strong attention to detail. A creative problem-solver who can think independently. Capable of working under tight deadlines while maintaining high-quality standards. A team player who can contribute effectively both individually and collaboratively

Reviewing SerDes standards to develop analog sub-block specifications. Identifying and refining circuit architectures to achieve optimal power, area, and performance targets. Proposing design and verification strategies that efficiently use simulator features to ensure the highest quality design. Overseeing physical layout to minimize the effects of parasitics, device stress, and process variation. Presenting simulation data for peer and customer review. Documenting design features and test plans. Consulting on the electrical characterization of your circuit within the SerDes IP product and proposing solutions for post-silicon design updates. The Impact You Will Have: Contributing to the development of high-performance SerDes IP that meets industry standards. Optimizing power, area, and performance of analog circuits, driving efficiency and innovation. Ensuring high-quality designs through meticulous verification strategies and simulator features. Improving the reliability and robustness of integrated circuits through careful layout oversight. Enhancing customer satisfaction by presenting comprehensive simulation data and supporting design reviews. Facilitating post-silicon design updates with your expertise in electrical characterization. What You ll Need: BE+6 years of relevant experience or MTech+4 years of relevant experience in Electrical Engineering, Computer Engineering, or a related field. In-depth familiarity with transistor-level circuit design and sound CMOS design fundamentals. Detailed design experience with at least one SerDes sub-circuit and familiarity with several others (e.g., receive equalizers, samplers, voltage/current-mode drivers, serializers, deserializers, VCO, phase mixer, DLL, PLL, bandgap reference, ADC, DAC). Aware of ESD issues and circuit techniques. Familiarity with custom digital design and high-speed logic paths. Knowledge of design for reliability (EM, IR, aging, etc.). Experience with tools for schematic entry, physical layout, and design verification. Hands-on experience with physical layout of high-speed circuits is a plus. Knowledge of SPICE simulators and simulation methods. Proficiency in Verilog-A for analog behavioral modeling and simulation-control / data-capture. Experience with scripting languages such as TCL, Perl, C, Python, or MATLAB. Who You Are: A highly analytical thinker with a strong attention to detail. A collaborative team player who thrives in a diverse work environment. Excellent communicator with strong documentation skills. A proactive problem-solver who can identify and implement solutions effectively. Adaptable and open to learning new technologies and approaches

You are a highly skilled and experienced Analog Design Engineer with a passion for developing cutting-edge technology. With a strong foundation in Electrical or Computer Engineering, you have honed your expertise in transistor-level circuit design and are adept at working with high-speed analog integrated circuits. Your deep understanding of CMOS design fundamentals and familiarity with various SerDes sub-circuits make you an invaluable asset to any team. You thrive in collaborative environments, working seamlessly with cross-functional teams of analog and digital designers. Your meticulous approach ensures optimal power, area, and performance targets are met, and your innovative design strategies push the boundaries of what is possible. You are not only technically proficient but also possess excellent communication and documentation skills, allowing you to effectively share your ideas and results with peers and customers. Your proactive attitude and problem-solving abilities make you a go-to person for post-silicon design updates and electrical characterization. In summary, you are a seasoned professional ready to take on the challenges of high-speed analog integrated circuit design in the latest FinFET process nodes. What You ll Be Doing: Review SerDes standards to develop analog sub-block specifications. Identify and refine circuit architectures to achieve optimal power, area, and performance targets. Propose design and verification strategies that efficiently use simulator features to ensure the highest quality design. Oversee physical layout to minimize the effect of parasitics, device stress, and process variation. Present simulation data for peer and customer review. Document design features and test plans. Consult on the electrical characterization of your circuit within the SerDes IP product. Propose solutions for post-silicon design updates. The Impact You Will Have: Drive innovation in high-speed analog integrated circuit design. Ensure optimal performance, power efficiency, and area utilization of our products. Contribute to the development of industry-leading SerDes IP. Enhance the reliability and quality of our analog sub-blocks. Support the successful integration of SerDes IP into customer products. Foster collaboration and knowledge sharing within the R&D team. Influence design strategies and best practices within the organization. What You ll Need: BE with 5+ years of relevant experience or MTech with 4+ years of relevant experience in Electrical Engineering or Computer Engineering. In-depth familiarity with transistor-level circuit design and sound CMOS design fundamentals. Detailed design experience with at least one, and familiarity with several other SerDes sub-circuits. Awareness of ESD issues and circuit techniques for addressing them. Familiarity with custom digital design and high-speed logic paths. Knowledge of design for reliability, including EM, IR, and aging considerations. Experience with tools for schematic entry, physical layout, and design verification. Hands-on experience with physical layout of high-speed circuits is a plus. Proficiency with SPICE simulators and simulation methods. Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control / data-capture. Experience with scripting languages such as TCL, Perl, C, Python, or MATLAB is desired. Who You Are: Collaborative and able to work effectively in a team environment. Detail-oriented with a strong focus on quality and reliability. Proactive problem-solver with innovative design strategies. Excellent communicator with strong documentation skills. Adaptable and able to thrive in a fast-paced, dynamic environment.

Developing next-generation high-speed memory interface PHY IPs (DDR/HBM/UCIe) Executing projects in advanced technologies with a focus on analytical and problem-solving skills Designing high-speed IOs for memory interface PHY IP in CMOS/FinFET/GAA Collaborating with cross-functional teams globally to achieve project goals Ensuring product quality and efficiency in all design tasks Staying updated with the latest industry standards and technological advancements The Impact You Will Have: Driving the development of innovative high-speed memory interface PHY IPs Contributing to the integration of advanced capabilities in SoCs Enhancing the performance, power efficiency, and size optimization of target applications Reducing risk and accelerating time-to-market for differentiated products Collaborating with global teams to deliver high-quality products Setting industry benchmarks for advanced analog design technologies What You ll Need: BTech/MTech degree in a relevant field 3+ years of experience in analog design fundamentals and device physics Proficiency in high-speed IO designs in advanced technologies Experience with ESD and reliability concepts Knowledge of JEDEC requirements for memory interfaces and standards Familiarity with signal integrity and/or power integrity is a plus Who You Are: An analytical thinker with strong problem-solving skills A collaborative team player with excellent communication and interpersonal skills Detail-oriented and capable of executing tasks with high precision and efficiency Adaptable and eager to learn new technologies and industry standards Passionate about innovation and technological advancement

"> Search Jobs Find Jobs For * Designing and developing DDR I/O circuits to meet performance and power specifications. * Collaborating with cross-functional teams to integrate analog circuitry into SoCs. * Executing circuit design tasks with a focus on product quality and efficiency. * Conducting layout reviews and ensuring adherence to design methodologies. * Participating in design reviews and providing technical insights. * Staying updated with the latest advancements in CMOS processes and deep submicron technologies. The Impact You Will Have: * Enhancing the performance and efficiency of our silicon IP portfolio. * Contributing to the rapid integration of advanced capabilities into SoCs. * Reducing the time-to-market and risk for our customers products. * Driving innovation in analog design and setting new industry standards. * Strengthening Synopsys position as a leader in chip design and verification. * Empowering the development of high-performance, differentiated products. What You ll Need: * BTech/MTech in Electrical Engineering or a related field. * 4+ years of experience in CMOS circuit design and layout methodology. * Strong knowledge of deep submicron process technologies. * Familiarity with ASIC design flow and JEDEC standards for DDR interfaces. * Excellent written and verbal communication skills. Who You Are: * A collaborative team player with a proactive approach. * Detail-oriented with a commitment to quality and efficiency. * Innovative and adaptable, always seeking to learn and grow. * Effective communicator, able to convey technical information clearly. * Problem-solver with strong analytical skills.

Review SerDes standards to develop novel transceiver architectures and sub-block specifications. Investigate and develop circuit architectures that address architectural bottlenecks and lead to revolutionary improvements in power, area and performance targets. Work across project and department teams to streamline design and verification strategies ensure overall design quality, efficiency and performance. Oversee physical layout to minimize the effect of parasitics, device stress, and process variation. Present & review simulation data from internal project teams. Present results externally at industry panels or at customer reviews. Document design features and test plans. Consult on the overall electrical characterization of the SerDes IP product. Analyze customer silicon data for design enhancements. Propose solutions for post-silicon design updates. Job Requirements MTech/MS with 12+ years, Btech/BS with 14+ years of practical analog IC design experience; degree in Electrical Engineering or Computer Engineering or other relevant field of study Experience with FinFET technologies In depth familiarity with transistor level circuit design - sound CMOS design fundamentals, experience with CMOS tape-outs Good understanding of Multi Gbps range High speed designs including PAM4 SerDes Architectures Extensive design experience with at least one, and familiarity with several other SerDes sub-circuits (ie. TX, RX ,adaptive Equalizers-(FIR, DFE, CTLE), PLL, DLL, BGR, Regulators, Injection locked oscillators, ADC, DAC etc) Experience with analog/digital interactions for optimizing circuit performance (calibration, adaptation, timing-handoff, etc) Aware of ESD issues (ie. circuit techniques, layout) Familiarity with custom digital design (ie. high speed logic paths) Knowledge of design for reliability (ie. EM, IR, aging, self heating etc ) Knowledge of layout effects (ie. matching, reliability, proximity effects, etc ) Experience with tools for schematic entry, physical layout, and design verification Knowledge of SPICE simulators and simulation methods Exposure to scripting for post processing of simulation results (ie. TCL, PERL, MATLAB etc ) Some knowledge of system level budgeting (ie. jitter, amplitude, noise, etc ) Aware of signal integrity issues (ie. effects of packaging, board parasitics, crosstalk, noise) Good communication and documentation skills