You are a highly motivated Staff Engagement Applications Engineer with over 4+ years of hands-on experience in synthesis or place and route (P&R). You have a robust understanding of the Synthesis concepts and are eager to work closely with R&D on driving product and methodology development. You thrive in dynamic environments and possess excellent communication skills, including a strong command of English. Your background in EE/CS, coupled with your experience with EDA tools like DC, FM, ICC2, and Fusion Compiler, makes you an ideal fit for this role. What You ll Be Doing: Providing Customer Support and Collaborating with R&D teams to drive product development for wide deployment. Demonstrating differentiated PPA results to showcase our technologys superiority. Providing technical support to key global customers to address PPA bottlenecks and design challenges on the most advanced designs. Aggressively engaging in worldwide critical benchmarks and deployments to ensure the highest quality and performance of designs. Utilizing scripting languages such as Perl and Tcl for automation and optimization tasks. Staying updated with the latest advancements in ASIC design flow, VLSI, and CAD development to continually improve processes. The Impact You Will Have: Enhancing the performance and efficiency of Fusion Compiler designs. Driving innovations that contribute to the success of Synopsys cutting-edge technologies. Providing critical support that helps key customers overcome their PPA challenges. Contributing to the development of new features that keep Synopsys at the forefront of the industry. Improving the overall quality and reliability of our products through meticulous design and optimization. Fostering strong relationships with global customers, reinforcing Synopsys reputation as a leader in chip design and software security. What You ll Need: BS/MS in Electrical Engineering or Computer Science with 4+ years of relevant experience. Hands-on experience with synthesis and place and route (P&R) tools. Proficiency with EDA tools such as DC, FM, ICC2, and Fusion Compiler. Knowledge of advanced placement and routing rules. Experience with scripting languages like Perl and Tcl. Strong understanding of ASIC design flow, VLSI, and CAD development. Never give-up attitude and flexibility in supporting worldwide engagements. Who You Are: Excellent communicator with strong command of English. Highly motivated and self-driven. Detail-oriented with a focus on quality and performance. A team player who thrives in collaborative environments. Adaptable and eager to learn new technologies and methodologies.

As our ideal candidate, you are a seasoned professional with a deep understanding of CMOS analog and mixed-signal Layout Design Engineering. You thrive in a collaborative environment and are passionate about pushing the boundaries of technology. With over 5 years of experience, you have honed your skills in designing complex PLLs, VCOs, charge pumps, and high-speed digital circuits Layout. You are detail-oriented, capable of coordinating with various teams, and have a proven track record of delivering high-quality designs. Your strong foundation in electrical engineering, combined with your innovative mindset, allows you to tackle diverse problems creatively and effectively. With excellent communication skills, you can articulate complex technical concepts to both technical and non-technical stakeholders, ensuring seamless collaboration and project success. What You ll Be Doing: Collaborate with cross-functional teams to develop and implement layout designs for analog and mixed-signal (A&MS) integrated circuits in PLL and other IP Create and optimize layout designs using industry-standard EDA tools. Perform physical verification and design rule checks to ensure design integrity and manufacturability. Define, design and develop complex RF clock path Participate in design reviews and provide feedback to improve design quality. Work closely with circuit designers to understand design specifications and constraints. Contribute to the development and enhancement of layout design methodologies and best practices. Stay updated with the latest industry trends and advancements in A&MS layout design. The Impact You Will Have: Ensure the highest quality and performance of our analog and mixed-signal integrated circuits. Drive innovation by developing cutting-edge layout designs that push the boundaries of technology. Enhance the manufacturability and reliability of our products through meticulous design and verification processes. Contribute to the overall success of our projects by providing valuable feedback during design reviews. Improve design methodologies and best practices, fostering a culture of continuous improvement. Support the growth and development of junior engineers by sharing your expertise and knowledge. What You ll Need: Bachelors or Masters degree in Electrical Engineering or a related field. 7+ years of experience in A&MS layout design for integrated circuits. Hands physical design experience of passive elements used in PLL RC filter, LC oscillator Basic knowledge of PLL operating blocks Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. Exceptional knowledge of layout design methods, techniques, and methodologies. Experience with physical verification tools, such as Calibre or Assura. Understanding of semiconductor process technologies and their impact on layout design. Excellent problem-solving and systematic skills. Ability to work effectively in a team-oriented env Who You Are: Innovative thinker with a passion for technology and problem-solving. Excellent communicator, capable of articulating complex concepts clearly. Detail-oriented with a strong focus on quality and precision. Collaborative team player who thrives in a dynamic work environment. Adaptable and able to manage multiple priorities effectively

You will be part of the industry s leading SDC Management product engineering team. Responsibilities include working with customers to ensure that our SDC Constraints solution meets their expectations; working on design methodologies that integrate our SDC constraints solution with other Synopsys products. You will track customer engagements, communicate status with Marketing and Upper Management. You will prepare and deliver technical presentations to customers, FAEs. You will develop customer training material related to our SDC Constraints solution. You will routinely meet with customers and communicate their key priorities internally. You will provide technical direction to our R&D team, champion and prioritize key customer requests. Desired Skills and Experience: Proficiency with STA, SDC. Proficiency with RTL, System Verilog. Strong understanding of front-end EDA design methodologies. Strong Perl, Tcl or Python scripting skills. Prior experience with logic synthesis tools is required. Prior experience using or supporting SDC tools would be a significant plus. Prior experience with RTL simulation, SVA would be a plus. Prior experience supporting front-end EDA tools would be a plus. Sound communication skills, verbal and written. Ability to produce product requirement documents. BS EE/CE. 4 years experience with STA/Synthesis.

An Analog Design engineer works on conceptualizing, designing and productizing state of the art analog sensors. We are seeking an experienced, highly motivated, and high-caliber individual to work on design of on-chip Process, Voltage, Temperature, Current and Droop sensors as part of PVT sensor group. This individual should have strong technical experience in full custom analog/mixed-signal circuit design, circuit simulations, custom layout and post-silicon characterization. Additional responsibilities include: Development of new solutions in the field of on-die monitoring Liaising with layout team to achieve best possible engineering solution Deployment of new sensors into test chips and post-silicon characterization Guiding more junior engineers and tracking their work Job Requirements Design oriented and forward-looking thought process Sound knowledge of custom Analog/AMS design techniques, implementation and verification B.Tech. or M.Tech. degree in Electrical Engineering with 5+ years of relevant industry experience or Phd with relevant experience. Awareness of full custom layout techniques Exposure to advanced process challenges, including ESD and Reliability Exposure to architecture, design and verification of PVT, Oscillators, Bandgap, PLLs, LDOs, ADCs, Amplifiers, PHYs and other Mixed-signal blocks Excellent teamwork, communication, mentoring, and interpersonal skills with both internal teams and external customers Preferred skills : Strong custom design experience - specification, circuit design description and schematics Hands on experience with circuit design & simulation tools, IC design CAD packages - from any EDA vendor Strong understanding of SPICE simulator concepts and simulation methods Familiar with circuit simulation tools like PrimeSim, FineSim, HSPICE or similar Must have prior experience with Custom Compiler or equivalent schematic & Layout editor tools Experience with statistical design methodology like generating and analyzing Monte-Carlo results Awareness of post-layout extraction & simulation, testing in conjunction with silicon validation Demonstrated technical expertise in the productization of advanced technologies

You are a highly motivated and experienced Analog Design Engineer with a passion for developing state-of-the-art analog sensors You thrive in a collaborative environment and have a knack for solving complex problems Your strong technical expertise in full custom analog/mixed-signal circuit design, circuit simulations, custom layout, and post-silicon characterization sets you apart You are a forward-thinking individual who is always looking for innovative solutions and has excellent communication and mentoring skill You possess a BTechor MTech degree in Electrical Engineering with over 5 years of relevant industry experience, or a PhD with relevant experience You have a deep understanding of custom Analog/AMS design techniques, implementation, and verification, and you are familiar with the challenges of advanced processes, including ESD and reliability What You ll Be Doing: Developing new solutions in the field of on-die monitoring. Liaising with the layout team to achieve the best possible engineering solutions. Deploying new sensors into test chips and conducting post-silicon characterization. Guiding and mentoring junior engineers and tracking their work. Conceptualizing, designing, and productizing state-of-the-art analog sensors. Collaborating with cross-functional teams to ensure successful project execution. The Impact You Will Have: Contributing to the development of next-generation intelligent in-chip sensors. Enhancing the performance, power, area, schedule, and yield of our customers products. Improving the reliability of various target applications through innovative solutions. Advancing the field of on-die monitoring with cutting-edge technologies. Driving the integration of full hardware IP, test, and end-to-end solutions. Supporting the continuous technological innovation that powers the Era of Smart Everything. What You ll Need: Strong technical experience in full custom analog/mixed-signal circuit design. Proficiency in circuit simulations and custom layout techniques. Experience with post-silicon characterization and deployment of new sensors. Sound knowledge of custom Analog/AMS design techniques, implementation, and verification. Awareness of advanced process challenges, including ESD and reliability. Who You Are: A forward-thinking engineer with a design-oriented mindset. An excellent team player with strong communication and interpersonal skills. A mentor who can guide and support junior engineers. A problem solver who thrives in a collaborative environment. A lifelong learner who stays updated with the latest industry trends and technologies.

* Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc ) * Generate verification test plan, verification environment documentation and test environment usage documentation * Define, develop, and verify complex UVM verification environments * Evaluates and exercises various aspects of the development flow. May include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modelling, and verification coverage metrics (functional coverage and code coverage) * Collaborate with architect, designers , VIP team to accomplish tasks. * Identify design problems, possible corrective actions and/or inconsistencies on documented functionality * Work with peers to improve methodologies and improve execution efficiency. * Adhere to quality standards and good test and verification practices. * Work as a lead, mentor junior engineers, and help them in debugging complex problems. * Able to Support Customer issues, by their reproduction and analysis. * Should be able multitask between different activities. Key Qualifications * Proven desire to learn and explore new state of the art technologies * Demonstrate good written and spoken English communication skills * Demonstrate good review and problem-solving skills * Knowledgeable with Verilog, VHDL and/or SystemVerilog * Knowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus * Understanding of verification methodology such as UVM . * Good organization and communication skills * Be a solution provider. * 8+ years of relevant experience

You are a seasoned ASIC Digital Design Engineer with a strong background in the design of IP Cores or SoC Designs. You have a passion for innovation and a desire to work on cutting-edge technology that powers the Era of Smart Everything. With a degree in Electrical Engineering and substantial experience in the field, you are well-versed in various protocols such as VESA-DSC, AMBA, SD/eMMC, DDR, PCIe, Ethernet, USB, and MIPI. You excel in creating micro-architecture and detailed design documents from functional specifications and have hands-on experience with Verilog/System Verilog coding and simulation tools. Your expertise in synthesis flow, static timing flows, and formal checking makes you a valuable asset to any team. You possess excellent communication skills, are a team player, and have a knack for problem-solving. Inclusion and diversity are important to you, and you thrive in a collaborative, multi-site environment. What You ll Be Doing: Understand standard specifications and functional specifications to create architecture, micro-architecture, and detailed design documents for medium to high complexity components. Contribute individually to the design tasks, including RTL coding, debugging, and verification coverage improvement. Utilize Low Power Design Methodology and automotive safety standards in your designs. Create and review designs for the DesignWare family of synthesizable cores in various protocol areas. Perform technical reviews of functional specifications, micro-architecture, and RTL code. Analyze coverage metrics and improve them by defining additional test cases in a directed environment. Collaborate with teams across multiple sites worldwide in a project and team-oriented environment. The Impact You Will Have: Drive innovation in chip design and verification, contributing to the development of advanced technologies. Enhance the performance, power efficiency, and size optimization of SoC designs. Reduce risk and speed up time-to-market for differentiated products. Ensure the reliability and robustness of IP cores through rigorous design and verification processes. Contribute to the development of industry-leading silicon IP solutions. Collaborate with a global team to achieve common goals and deliver high-quality results. What You ll Need: BSEE in Electrical Engineering with 8+ years of relevant experience or MSEE with 7+ years of relevant experience. Experience in designing IP Cores or SoC Designs. Knowledge of protocols such as VESA-DSC, AMBA, SD/eMMC, DDR, PCIe, Ethernet, USB, and MIPI. Ethernet protocol knowledge is highly preferred. Hands-on experience with creating micro-architecture and detailed designs from functional specifications. Proficiency in Verilog/System Verilog coding and simulation tools. Experience with synthesis flow, static timing flows, Lint, CDC, and formal checking. Knowledge of revision control environments like Perforce and scripting languages like Perl/Shell. Who You Are: Excellent communication skills and a team player. Strong problem-solving abilities. Detail-oriented with a focus on quality and precision. Adaptable and able to work in a fast-paced, multi-site environment. Committed to fostering an inclusive and diverse workplace

* Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification of all its functions, covering both the Controller and PHY. * Reporting metrics and driving improvements in Emulation IP. * Using your expertise to drive requirements for the Emulation IP and ensure its correct usage and deployment in verification strategies for both Controller and PHY. * Staying ahead of evolving standards, understanding future changes, specification errata, and driving this understanding into both the Emulation IP and Design IP teams. * Reviewing test plans in both Emulation IP and Design IP to ensure they deliver the required function, feature, and quality to be best in class. The Impact You Will Have: * Enhancing cross-functional collaboration to improve product quality and end customer satisfaction. * Changing the mindset in the way we use Emulation IP in validating digital designs and architectures. * Driving innovation in defining requirements for IP product development, in the context of Emulation. * Evolving and integrating best-in-class methodologies within the organization. * Standardizing and optimizing workflows to increase efficiency and compliance. What You ll Need: * 10+ years of relevant experience. * Results-driven mindset. * Exposure on advanced protocols like PCIe and DDR interfaces. * Experience with Zebu in the context of technology and IP verification. * Proven track record in IP product development, specifically emulation. * Experience in cross-functional collaborations. * Excellent communication skills and a beacon for change. * Adaptability and comfort in a matrixed, international environment.

You are a highly skilled and experienced engineer with a deep understanding of synthesis, timing closure, power optimization, and constraints management. You have a proven track record of working on advanced nodes under 5nm and are proficient in low-power, high-performance design. Your familiarity with RTL, DFT, LDRC, TCM, VCLP, and PTPX gives you an edge in tackling complex design challenges. You are adept at scripting languages such as TCL, Perl, and Python, and hold a BS or MS in Electrical Engineering or a related field with over 9 years of relevant experience. You thrive in a dynamic environment, constantly seeking to push the boundaries of technology and improve quality of results. Your ability to work both independently and collaboratively makes you an invaluable asset to any team. What You ll Be Doing: Developing innovative methodologies for implementing high-performance CPUs, GPUs, and interface IPs. Utilizing advanced technologies and tool features to enhance quality of results and streamline the implementation process. Contributing to the development and implementation of power, performance, and area (PPA) methodologies for complex IPs. Working with industry-leading Synopsys tools such as RTLA and Fusion Compiler to solve critical design challenges. Collaborating with a global team to stay ahead of technological advancements and design complexities. Driving continuous improvement in PPA and turnaround time (TAT) metrics. The Impact You Will Have: Advancing the state-of-the-art in high-performance core and IP implementation. Enhancing the performance and efficiency of Synopsys design methodologies and tools. Enabling the development of cutting-edge semiconductor technologies at advanced nodes. Contributing to the successful delivery of high-quality, high-performance IPs to the market. Driving innovation and pushing the boundaries of what is possible in chip design. Supporting Synopsys mission to lead in chip design, verification, and IP integration. What You ll Need: Deep knowledge of synthesis, timing closure, power optimization, and constraints management. Experience with low-power, high-performance design at advanced nodes under 5nm. Proficiency in RTL, DFT, LDRC, TCM, VCLP, and PTPX. Familiarity with scripting languages such as TCL, Perl, and Python. BS or MS in Electrical Engineering or a related field with 9+ years of relevant experience.

Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification of all its functions, covering both the Controller and PHY. Reporting metrics and driving improvements in Emulation IP. Using your expertise to drive requirements for the Emulation IP and ensure its correct usage and deployment in verification strategies for both Controller and PHY. Staying ahead of evolving standards, understanding future changes, specification errata, and driving this understanding into both the Emulation IP and Design IP teams. Reviewing test plans in both Emulation IP and Design IP to ensure they deliver the required function, feature, and quality to be best in class. The Impact You Will Have: Enhancing cross-functional collaboration to improve product quality and end customer satisfaction. Changing the mindset in the way we use Emulation IP in validating digital designs and architectures. Driving innovation in defining requirements for IP product development, in the context of Emulation. Evolving and integrating best-in-class methodologies within the organization. Standardizing and optimizing workflows to increase efficiency and compliance. What You ll Need: 10+ years of relevant experience. Results-driven mindset. Exposure on advanced protocols like PCIe and DDR interfaces. Experience with Zebu in the context of technology and IP verification. Proven track record in IP product development, specifically emulation. Experience in cross-functional collaborations. Excellent communication skills and a beacon for change. Adaptability and comfort in a matrixed, international environment

We are seeking innovative and out-of-the-box thinking Design For Test (DFT) Engineers to be a part of the Fast Solution Team under the Test Group at Synopsys. You are someone who thrives in a project-oriented environment, delivering comprehensive DFT solutions ranging from integration to silicon bring-up for customers designing digital ICs of varying complexity. You excel in assessing customer methodologies and flows, gathering requirements, and proposing solutions. You are adept at providing technical support to ensure customer success and satisfaction, winning new customers through product demonstrations, evaluations, and competitive benchmarking. You are skilled in resolving technical problems, training, and account management, and you can interact effectively with end-users at customer sites and with first-level managers. You are also responsible for working with Solution Architects to develop and productize the next-gen test technologies. Your role involves prototyping new methodologies, analyzing gathered data, identifying the viability of technology, and presenting the findings under the guidance of a Solution Architect. What You ll Be Doing: Providing expertise for test solutions during design planning, budgeting, and implementation. MBIST implementation and validation, including BIST architecture planning, memory grouping, pattern generation, validation, silicon bring-up, diagnostics analysis, and debug. Participating in customer s design and flow reviews. Driving, prototyping, and developing new Design for Test methodologies. Multitasking across various issues and priorities to help customers exploit new technologies. Collaborating with Solution Architects to develop and productize next-gen test technologies. The Impact You Will Have: Enhancing Synopsys ability to deliver cutting-edge test solutions that meet customer needs. Contributing to the successful integration and silicon bring-up of complex digital ICs. Ensuring high customer satisfaction through effective technical support and problem resolution. Driving innovation in test methodologies and technologies. Supporting the development of next-gen test technologies that push the boundaries of whats possible. Playing a key role in winning new customers and expanding Synopsys market presence. What You ll Need: Minimum BS+10 years of relevant experience/MS+8 years of relevant experience in Electrical Engineering, Computer Engineering, or other relevant fields of study. Experience with RTL coding, DFT insertion, ATPG, MBIST architecture planning, insertion, validation, pattern generation, and silicon bring-up. Excellent knowledge of memory BIST flows, memory fault models, MBIST algorithms, hard/soft repair, and eFuse repair flow. Experience in handling memory BIST for large, complex SoCs with various IPs. Exposure to MBIST of automotive designs is a plus. Good understanding of protocols like 1149.1, 1500, 1687.

Designing and verifying digital and mixed-signal circuits for NRZ and PAM-based SerDes products. Collaborating with a team of experienced engineers to deliver high-performance mixed-signal designs. Developing and executing structured firmware development, verification, and documentation processes. Performing functional and performance tests on prototype test-chips. Communicating effectively with different design groups and customer support teams. Balancing good design quality while meeting tight deadlines. The Impact You Will Have: Contributing to the development of cutting-edge SerDes products that drive the innovations of tomorrow. Ensuring high-performance and reliable mixed-signal designs that meet unique performance, power, and size requirements. Accelerating the integration of more capabilities into an SoC, helping customers bring differentiated products to market quickly with reduced risk. Enhancing Synopsys reputation as a leader in chip design and software security. Driving the success of our Silicon IP business by delivering high-quality mixed-signal designs. Playing a key role in the continuous technological innovation at Synopsys. What You ll Need: BSEE or MSEE plus a minimum of 5 years industry experience in Silicon Bring up and Functional Validation. Experience with structured firmware development, verification, and documentation processes. Proficiency in digital logic design, simulation, and debug using Verilog and VCS. Demonstrated experience executing projects from start to completion. Good communication skills for interacting between different design groups and customer support teams

Design and implement Data Ingestion & Processing pipelines for our Sentaurus Calibration Workbench (SCW) - Format support, validation, DB with search/filters, AI/ML-driven analysis. Integrate core TCAD simulation engines with SCW - Optimize connectivity to reduce turnaround time (TAT), improve scalability, quality of results (QoR), and ease-of-use (EoU) Collaborate closely with the product application engineering (PAE) team to ensure functionality and quality requirements are met. Collaborate closely with the front-end team to ensure backend features are seamlessly integrated into the GUI for end-users. The Impact You Will Have: Drive advancements in TCAD calibration automation, leading to significant improvements in simulation efficiency and accuracy. Enhance the user experience by supporting integration of backend features into a user-friendly GUI, enabling seamless deployment of calibration workflows to customers. Support the creation of innovative solutions that address complex semiconductor design challenges, contributing to the success of our customers. Streamline the TCAD calibration process, reducing TAT and improving overall productivity for both internal teams and customers. Foster collaboration and knowledge sharing within the team, driving continuous improvement and innovation in SCW. What You ll Need: MS or PhD in Computer Science, Software Engineering, Electrical Engineering, or equivalent. 4+ years of hands-on experience in software development with solid programming skills in C++ and Python. Solid data analysis knowledge and skills. Familiarity and hands-on experience with ML applied to data analysis and optimization. Strong desire to learn and explore new technologies. English language working proficiency and communication skills allowing teamwork in an international environment. Willingness to work in a distributed international team.

Review SerDes standards to develop analog sub-block specifications. Identify and refine circuit architectures to achieve optimal power, area, and performance targets. Propose design and verification strategies that efficiently use simulator features to ensure the highest quality design. Oversee physical layout to minimize the effect of parasitics, device stress, and process variation. Present simulation data for peer and customer review. Document design features and test plans. Consult on the electrical characterization of your circuit within the SerDes IP product. Propose solutions for post-silicon design updates. The Impact You Will Have: Drive innovation in high-speed analog integrated circuit design. Ensure optimal performance, power efficiency, and area utilization of our products. Contribute to the development of industry-leading SerDes IP. Enhance the reliability and quality of our analog sub-blocks. Support the successful integration of SerDes IP into customer products. Foster collaboration and knowledge sharing within the R&D team. Influence design strategies and best practices within the organization. What You ll Need: BE with 8+ years of relevant experience or MTech with 6+ years of relevant experience in Electrical Engineering or Computer Engineering. In-depth familiarity with transistor-level circuit design and sound CMOS design fundamentals. Detailed design experience with at least one, and familiarity with several other SerDes sub-circuits. Awareness of ESD issues and circuit techniques for addressing them. Familiarity with custom digital design and high-speed logic paths. Knowledge of design for reliability, including EM, IR, and aging considerations. Experience with tools for schematic entry, physical layout, and design verification. Hands-on experience with physical layout of high-speed circuits is a plus. Proficiency with SPICE simulators and simulation methods. Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control / data-capture. Experience with scripting languages such as TCL, Perl, C, Python, or MATLAB is desired. Who You Are: Collaborative and able to work effectively in a team environment. Detail-oriented with a strong focus on quality and reliability. Proactive problem-solver with innovative design strategies. Excellent communicator with strong documentation skills. Adaptable and able to thrive in a fast-paced, dynamic environment

Lead the architecture and development of analog/mixed-signal blocks for PCIe 6 and PCIe 7 PHY designs. Ensure designs meet PCIe protocol standards, optimizing for performance, power, and area targets. Oversee the porting of PHY designs to different technology nodes, maintaining signal integrity and performance. Collaborate with cross-functional teams to integrate analog circuits into larger SerDes PHY systems. Develop and implement verification strategies for high-speed analog/mixed-signal circuits using advanced simulation tools. Supervise physical layout to minimize parasitics, device stress, and process variation impacts. Review simulation and measurement data for design validation and compliance with PCIe standards. Provide technical leadership and mentorship to junior engineers in analog/mixed-signal design best practices. Document design features, specifications, test plans, and methodologies for future reference. Collaborate with the characterization team to validate the electrical performance of circuits in silicon. The Impact You Will Have: Drive the development of next-generation PCIe 6 and PCIe 7 PHY designs, contributing to the advancement of high-speed interface technology. Ensure that Synopsys analog/mixed-signal circuits meet stringent industry standards, enhancing the companys reputation for excellence. Facilitate the seamless integration of analog circuits into complex SerDes PHY systems, improving overall system performance. Mentor and develop junior engineers, fostering a culture of continuous learning and innovation within the team. Contribute to the successful porting of PHY designs across different technology nodes, ensuring versatility and adaptability. Enhance the companys design verification processes, leading to more robust and reliable high-speed analog/mixed-signal circuits. What You ll Need: PhD with 5+ years, or MTech/MS with 10+ years of experience in analog/mixed-signal circuit design, with a focus on high-speed interfaces such as PCIe 6/7 or SerDes PHY designs. Extensive experience in transistor-level design of high-speed analog building blocks, such as LDOs, Bandgap references, ADC/DAC, PLLs, DLLs. Proven silicon experience in developing PHY circuits that meet strict PCIe standards. Expertise in high-speed SerDes AFE (Analog Front-End) development, including CTLE and CDR design. Experience designing high-speed SerDes transmitters, with in-depth knowledge of equalization techniques (e.g., DFE, FIR filters, TX pre-emphasis). Strong background in jitter budgeting analysis, including understanding the sources of jitter and strategies for minimizing its impact on signal integrity. Extensive experience with the porting of PHY designs across different technology nodes. Strong expertise in CMOS technologies, including finFET and SOI processes. In-depth understanding of the PCIe protocol, signal integrity requirements, jitter performance, and high-speed clocking. Proven ability to supervise layout design to minimize the effects of parasitics, process variations, and electromigration. Demonstrated ability to lead and mentor design teams, working across departments to ensure successful project outcomes

Synopsys is looking for a highly motivated software engineer to help enable leading edge Macro characterization and validation solution by joining our characterization team As part of the R&D team, you will have a unique opportunity to explore a variety of areas within performance improvement, accuracy improvement of liberty models, large scale characterization, ranging from classification problems to complex regression models The complex software engineering requirements for Macro characterization, can make a huge difference in enabling next generation of characterization solution This dynamic, collaborative, and exciting environment offers plenty of opportunities for both broad exposure to new technologies, as well as the ability to learn deeply within specific modeling topics The responsibilities include: * Developing, Maintaining and improving software implementations * Working with field support team and customers to understand new technical requirements * Designing new architectures for a wide range of problem areas. * Collaborating with cross functional teams to enable complex flows across tools Qualification Requirements: * MS in CS/EE/physics/applied math or related fields with 6+ years, or PhD in related field. * Demonstrated analytical and problem-solving skills with strong desire to explore new technologies * Solid programming skills in C++ and Python and familiar with data structures and algorithms * Experience in numerical computation * Good communication skills and the ability to work in a team environment Nice to have: * Experience with transistor level circuit simulators, understanding of digital logic and/or Macro IP environment * Experience in computational lithography, image processing, or machine learning * Experience in the development of large, complex software projects * Strong background in mathematical or physical modeling

Driving the physical implementation of high-speed interface IPs and test-chips from RTL to GDS. Managing timing and physical sign-off to ensure successful project tape-outs. Collaborating with multiple functional groups, including front-end, analog, and CAD teams. Focusing on advanced SerDes developments, including the latest 56/112G PAM4 standards. Leading the physical design team to ensure on-time delivery of projects. Utilizing your software and scripting skills to enhance CAD automation methods. The Impact You Will Have: Contributing to the successful delivery of high-performance silicon IPs that power the Era of Smart Everything. Ensuring the integration of more capabilities into SoCs, meeting unique performance, power, and size requirements. Reducing the risk and time-to-market for differentiated products. Driving technological innovation through advanced SerDes development. Enhancing Synopsys reputation as a leader in chip design and verification. Supporting the companys mission to power the world s most advanced technologies for chip design and software security. What You ll Need: 10+ years of physical design experience with recent contributions to project tape-outs. Intimate understanding of the full design cycle from RTL to GDSII, including chip level. Experience with advanced FinFET nodes, TSMC 16 nanometer or below. Solid understanding of IC design, implementation flows, and methodologies for deep submicron design. Proven track record for technical steering of physical design teams for on-time delivery. Who You Are: Excellent communicator with the ability to engage with peer groups and customers. Autonomous and capable of making timely judgments. Proficient in software and scripting skills (Perl, Tcl, Python). Knowledgeable in CAD automation methods and industry standards in deep sub-micron designs. Able to travel internationally as required

Owning the complete physical implementation process at both block and chip levels. Delivering timing clean blocks and chip-level designs that meet design targets. Ensuring DRC, LVS, and IR closure for all designs. Setting up and evaluating all aspects of the physical design flow, including place and route, timing, PV, and IR. Collaborating closely with the frontend design team to resolve design issues. Executing project responsibilities from start to completion, contributing to moderately complex aspects of the project. The Impact You Will Have: Ensuring the delivery of high-quality, timing-clean designs that meet industry standards. Driving innovation in physical design methodologies and processes. Contributing to the development of cutting-edge technologies that shape the future. Enhancing the overall efficiency and effectiveness of the design team. Providing mentorship and guidance to junior engineers, fostering a culture of continuous learning and improvement. Strengthening Synopsys position as a leader in the semiconductor industry through your expertise and contributions. What You ll Need: MSEE/BSEE with 6+ years of related experience in ASIC physical design. In-depth understanding of physical design specialization, with working knowledge of one other related area. Strong problem-solving skills and creativity in resolving design issues. Experience in scripting using Tcl and Perl. Ability to execute project responsibilities independently and contribute to team-driven projects. Who You Are: Detail-oriented and committed to delivering high-quality work. Collaborative and able to work effectively in a team environment. Proactive and able to take ownership of tasks and projects. Excellent communicator, capable of networking with senior personnel. Mentor and guide to junior peers, sharing knowledge and expertise.

Reviewing Die, package, and PCB physical layout designs Modeling, simulating, and verifying high-speed interface performance against specifications Participating in the improvement of SI/PI methodology flows Collaborating and networking with other teams on task-oriented projects Independently driving SI/PI research and development activities Ensuring designs meet stringent performance, power, and size requirements The Impact You Will Have: Enhance the performance and reliability of high-speed interfaces Contribute to the development of cutting-edge technology in chip design Improve SI/PI methodology flows, increasing efficiency and accuracy Foster collaboration and innovation across globally distributed teams Drive research and development initiatives to stay ahead in the industry Support Synopsys mission to lead in the Era of Pervasive Intelligence What You ll Need: Bachelors or Masters degree in Electrical or Electronics Engineering Minimum of 8 years of relevant experience Proficient in Transmission line theory and time/frequency-domain analysis Experienced with SPICE and familiar with 3D field solvers Conversant with working of DDR and PCIe/Ethernet interfaces Good verbal and written English communication skills Experience in scripting languages such as Python and TCL is a plus Familiarity with both Windows and Linux operating system

Assisting internal stakeholders (marketing, sales team) with technical presentations and evaluating potential applications of Synopsys products to meet customer needs. Collaborating with internal and external stakeholders on technology and solution development, validation, customer engagement, and deployment. Providing technical assistance to customers, helping them solve their technical problems, and conducting tool training sessions. Working closely with the PrimeTime R&D team to support the adoption and continuous usage of PrimeTime. Engaging with field teams and customers on advanced technology engagements. Driving innovation and success in chip design through continuous technological advancements. The Impact You Will Have: Enhancing customer satisfaction by providing expert technical support and solutions. Driving the successful adoption and usage of PrimeTime, contributing to its market leadership. Collaborating with R&D and field teams to innovate and improve Synopsys products and solutions. Facilitating customer engagement and ensuring their technological needs are met effectively. Contributing to the development and validation of cutting-edge technologies and solutions. Playing a pivotal role in driving the success of Synopsys chip design initiatives. What You ll Need: BSEE/MS with minimum 12 years of relevant experience Proficiency in static timing analysis (STA) and advanced STA methodologies. Strong understanding of the full flow for chip design and EDA tools/flows. In-depth knowledge of 3DIC stacking, packaging, and their impact on timing analysis and closure. Experience with standard cells, MEM, IO IPs, and their library modeling and usage in flow. Proficiency in STA constraints, ECO, and power optimization flow. Hands-on experience with SPICE simulation and STA vs SPICE correlation. Knowledge of advanced CMOS technologies and FinFET technology at 5nm/3nm/2nm and beyond. Coding skills in TCL and Python; familiarity with C++ is a plus. Familiarity with industry-standard ASIC tools such as PT, ICC, Redhawk, and Tempus. Who You Are: Strong communicator and collaborator. Technically adept and detail-oriented. Innovative thinker with a passion for technology. Customer-focused with excellent problem-solving skills. Team player who thrives in a dynamic environment

Develop CMOS embedded memories such as SP SRAM, DP SRAM, Register File, and ROM: Design architecture and circuit implementation, especially ultra high speed, ultra low power, or high-density design portfolio. Perform schematic entry, circuit simulation, layout planning, layout supervision, design verification and validation. Interface with CAD and Frontend engineers for memory compiler automation, EDA model generation and full verification flow. Perform bit cell development and bit cell verification, and drive physical layout design and verification. Provide support and/or perform other duties as assigned and required In this role, the Senior Engineer will be part of team contributing to Different type of Architectures of embedded SRAM, Register files and ROM. As senior Engineer, the individual will be involved in challenging projects and drive it to completion in defined timelines. You will quickly ramp on the existing flow, understand the challenges, and produce the work plan. Your expertise in deep submicron technology and Finfet, SRAM design , processor design , Digital design flow and teamwork skills will be highly leveraged to guide activity across the entire cross-discipline, multi-site team. You will work with others to identify the issues, get buy-in on proposed solutions, and implement the solutions in time for the team to execute to schedule. Skills/Experience: BE/B.Tech/ME/M.Tech/MS in Electrical & Electronics Engineering from premium institute/university with minimum of 1 years of experience in VLSI Design Deep understanding of SRAM/Register File architectures and advanced custom circuit implementations. Exposure to full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation. Direct experience with the most advanced technology nodes. Familiarity with variation-aware design in nanometre technology nodes W mastery in scripting using Perl, python for automation . Fundamentals: Understanding of RC circuit of 1 st and 2 nd order. Basics of Digital design (realization of Boolean function using Gates, Mux etc) Fundamentals of Transfer function and its analysis for stability etc. Strong CMOS fundamentals Knowledge of CMOS fabrication Good digital design knowledge Exposure to basic analog fundamentals

Designing software to support large-scale geometric data analysis and high-performance computing for OPC solutions. Optimizing infrastructure for distributed computing, ensuring seamless GPU integration. Collaborating with development teams to ensure efficient data handling and computational resource allocation. Debugging and troubleshooting infrastructure issues related to production line integration. Maintaining and troubleshooting the tool to meet performance and scalability requirements. Regularly contributing to the cutting-edge of semiconductor development by enhancing software performance and scalability. The Impact You Will Have: Advancing the development of high-performance silicon chips and software content. Enabling leading IC manufacturing through efficient software solutions. Contributing to the optimization of infrastructure for distributed computing. Ensuring seamless integration and operation of infrastructure components. Improving software performance and scalability for large-scale data analysis. Enhancing the overall efficiency and effectiveness of semiconductor development processes. What You ll Need: M.S. or Ph.D. in Computer Science, Engineering, or the Physical Sciences. 6+ years of experience in software development, with a focus on computational geometry and distributed processing. Expertise in C++, Python, and distributed computing environments. Experience in debugging and troubleshooting production-related issues. Strong communication and collaboration skills to work as part of a global team. Who You Are: A proactive problem solver with a passion for innovation. Detail-oriented with a focus on optimizing performance and scalability. An effective communicator with the ability to collaborate across teams. A self-motivated individual who can work independently with limited supervision. A sophisticated professional with advanced knowledge and wide-ranging experience.

Leading the development of next-generation DDR/HBM/UCIe IP. Providing guidance and mentorship to team members, ensuring project schedules are met and problems are resolved efficiently. Acting as a project leader, contributing to complex aspects of IP development. Developing and maintaining project schedules, collaborating with cross-functional teams. Designing and verifying CMOS circuits and layouts. Implementing analog mixed-signal simulation strategies and ensuring signal integrity. The Impact You Will Have: Driving the development of cutting-edge IP that powers the future of technology. Enhancing the capabilities of SoCs, enabling faster integration and reduced risk for customers. Contributing to the success of Synopsys by delivering high-quality IP on time. Leading a team of talented engineers, fostering innovation and excellence. Ensuring the highest standards of product quality and efficiency. Playing a key role in the Era of Smart Everything, from AI to IoT. What You ll Need: BTech/MTech degree in a relevant field. 8+ years of experience in analog design. Knowledge of CMOS processes and deep submicron process technologies. Proficiency in CMOS circuit design and layout methodology. Familiarity with analog mixed-signal simulation strategies. Understanding of JEDEC requirements for DDR interfaces and standards. Strong project management and leadership skills. Excellent written and verbal communication skills. Who You Are: A natural leader with the ability to inspire and guide a team. An excellent problem solver with a keen analytical mind. A collaborative team player who thrives in a cross-functional environment. A detail-oriented individual with a commitment to quality and efficiency. A proactive communicator who can convey complex technical information clearly.

* Collaborate with cross-function al teams to develop and implement layout designs for analog and mixed-signal (A&MS) integrated circuits. * Create and optimize layout designs using industry-stand ard EDA tools. * Perform physical verification and design rule checks to ensure design integrity and manufacturabil ity. * Participate in design reviews and provide feedback to improve design quality. * Work closely with circuit designers to understand design specifications and constraints. * Contribute to the development and enhancement of layout design methodologies and best practices. * Stay updated with the latest industry trends and advancements in A&MS layout design. The Impact You Will Have: * Ensure the delivery of high-quality layout designs for PVT Sensor IP development, integral to SOC subsystems. * Enhance the manufacturabil ity and reliability of our silicon lifecycle monitoring solutions. * Drive innovation in layout design methodologies and best practices. * Collaborate effectively with circuit designers to meet design specifications and constraints. * Contribute to the overall success of the rapidly expanding PVT IP group. * Support Synopsys leadership in the market for process, voltage, temperature, current, and droop sensors. What You ll Need: * Bachelor s or master s degree in electrical engineering or a related field. * 5+ years of experience in A&MS layout design for integrated circuits. * Proficiency in industry-stand ard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. * Exceptional knowledge of layout design methods, techniques, and methodologies. * Experience with physical verification tools, such as Calibre or Assura. * Understanding of semiconductor process technologies and their impact on layout design. * Excellent problem-solvin g and systematic skills. * Ability to work effectively in a team-oriented environment. * Good communication and interpersonal skills.

Review SerDes standards to develop analog sub-block specifications. Identify and refine circuit architectures to achieve optimal power, area, and performance targets. Propose design and verification strategies that efficiently use simulator features to ensure the highest quality design. Oversee physical layout to minimize the effect of parasitics, device stress, and process variation. Present simulation data for peer and customer review. Document design features and test plans. Consult on the electrical characterization of your circuit within the SerDes IP product. Propose solutions for post-silicon design updates. The Impact You Will Have: Drive innovation in high-speed analog integrated circuit design. Ensure optimal performance, power efficiency, and area utilization of our products. Contribute to the development of industry-leading SerDes IP. Enhance the reliability and quality of our analog sub-blocks. Support the successful integration of SerDes IP into customer products. Foster collaboration and knowledge sharing within the R&D team. Influence design strategies and best practices within the organization. What You ll Need: BE with 8+ years of relevant experience or MTech with 6+ years of relevant experience in Electrical Engineering or Computer Engineering. In-depth familiarity with transistor-level circuit design and sound CMOS design fundamentals. Detailed design experience with at least one, and familiarity with several other SerDes sub-circuits. Awareness of ESD issues and circuit techniques for addressing them. Familiarity with custom digital design and high-speed logic paths. Knowledge of design for reliability, including EM, IR, and aging considerations. Experience with tools for schematic entry, physical layout, and design verification. Hands-on experience with physical layout of high-speed circuits is a plus. Proficiency with SPICE simulators and simulation methods. Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control / data-capture. Experience with scripting languages such as TCL, Perl, C, Python, or MATLAB is desired. Who You Are: Collaborative and able to work effectively in a team environment. Detail-oriented with a strong focus on quality and reliability. Proactive problem-solver with innovative design strategies. Excellent communicator with strong documentation skills. Adaptable and able to thrive in a fast-paced, dynamic environment.