Teralynx series of switching products are key to Marvell cloud and AI market. IFCS SDK provides an interface for customer for Teralynx products. It is one of the critical component of the Teralynx products. With growing number of roadmap products and customers, we need more people and a leader to manage a team of developers. What You Can Expect Lead and manage a team of R&D engineers involved in the development of cloud Datacenter products of Marvell switching products. Responsible for the planning, execution, and delivery of software for Marvell switching products Contribute to the development of project goals and schedules. Demonstrate leadership and execute projects across a highly distributed engineering team. Work with various cross-functional groups such as Architect, other development teams, QA/Validation, System Test, Product Management, Product Documentation, Customer teams Collaborate and execute working with teams across various sites Responsible to mentor and train the team Manage the engineering resource allocation. Recruit, retain, and develop top engineering talent. Foster an inclusive, collaborative, and high-performance work environment. What Were Looking For The Software Engineering senior manager will lead the software development team to deliver innovative, high-quality software solutions that meet business objectives. We are looking for technology passionate leaders with focus on execution and quality to help innovate and develop highly scalable and distributed embedded network software. This role requires a strategic thinker with strong leadership skills and a deep technical background. The ideal candidate will be Bachelor s degree in Computer Science, Engineering, or a related field (Master s degree preferred). 10+ years of experience in software development, with at least 3 years in a management / leadership role. Proven track record of managing and delivering complex software projects. Strong knowledge of software development methodologies Excellent problem-solving, analytical, and decision-making skills. Strong communication and interpersonal skills. Experience in L2 switching/forwarding areas such as LAG, VLAN, xSTP, LLDP, Link OAM, ARP, VxLAN, DC fabric switching, etc. Experience in L3 unicast/multicast routing protocols such as RIP, OSPF, IGMP, BGP, ISIS, etc. Experience in embedded platform software for switching/routing products.

This position is with ASIC design physical implementation (PD) team part of Central Engineering business unit at Marvell, Bangalore. This team as part of global Implementation team plays a key role in Netlist to GDS implementation, covering Synthesis, P&R, Timing, PV and Power implementation all custom ASICs for all the OEM s. We are looking for individuals with the domain of physical design having Block /Subsystem level implementation experience on hierarchical designs using industry standard tools. What You Can Expect Work with a global team on the physical design of complex chips at Block/Partition/Full-Chip level. You will also play a critical role in refining the methodology to enable an efficient and robust design process working closely with the methodology team. Your tasks will include performing synthesis, place and route, as well as timing analysis and closure on a given hierarchical design at block/partition/full-chip level. You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues. Collaboration with the frontend team will be crucial to ensure successful tapeouts. Additionally, your involvement with the global timing team will include debugging and resolving any block/partition level timing issues encountered at the Chip level. This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell. What Were Looking For Have completed a Bachelor s OR a Masters Degree in Electronics/Electrical/VLSI field and have atleast 15+ years of related professional experience in physical design at Partition/Subsystem/Chip level with a proven track record of successful tape-outs. In your coursework, you must have completed a course in digital electronics, CMOS design and projects that involved circuit design & analysis. Good understanding of standard RTL to GDS flows and methodology, experience in designing ICs at advanced technology nodes (e. g. , 7nm, 5nm, or below) is highly desirable. Working knowledge on any of the scripting in languages such as Perl, tcl, AWK and Python. Knowledge of Verilog/VHDL basics is an added advantage. Good communication skills and self-discipline contributing in a team environment. In-depth knowledge and hands-on experience with industry-standard physical design tools and methodologies, including synthesis, floor planning, placement, clock tree synthesis, routing, and physical verification.

Data Center Engineering Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. This group provides technology development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology and design. You will be working with this team to directly enable customer DFT requirements for Custom and Compute Businesses. What You Can Expect The position will be responsible for implementing and validation DFT/Test on complex IP and SOC for multiple Custom/Compute ASIC/SoC designs The execution involves Implementation of various DFT/DFX features, Scan/MBIST Insertion & Validation, ATPG , IP-DFT, STA, pattern generation & Post-Silicon Bringup and Debug for various designs in Custom/Compute space. In this position, the responsibility also includes mentoring, guiding and driving a small team of engineers enabling them for scaling across multiple designs. The position also involves definition and enhancement of DFT methodologies and tools to be able to benchmark them and enable new methodologies in the domain of DFT/Test. What Were Looking For Bachelor s degree in Computer Science, Electrical Engineering or related fields and 10+ years of related professional experience. Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 8+ years of experience. Hands on working experience in various stages of DFT-Execution SCAN Insertion / ATPG / MBIST / Validation / STA / IP-DFX / Post-Silicon Bringup/Debug Strong fundamentals in Digital Circuit Design and Logic Design is required Knowledge on various DFT/Test solutions Understanding of DFT Flows and Methodologies and Experience with Siemens/Synopsys/Cadence Tool set (Tessent/DC, Spyglass, Tmax, VCS/Genus, Modus, NCSim ) Prior experience in ASIC design is a plus Scripting skills using PERL, Tcl and C-Shell is plus

Inside Sales Representative will be responsible for managing customer leads from various sources by connecting with them through phone and email. This position will be responsible for the complete sales cycle - nurturing the lead.

Are you passionate about transforming data into actionable insights? Join our team at Infineon Technologies as a Staff Engineer in Data Engineering & Analytics! In this role, youll be at the forefront of harnessing the power of data to drive innovation and efficiency. Collaborate with experts, design robust data ecosystems, and support digitalization projects. If you have a strong background in data engineering, database concepts, and a flair for turning complex business needs into solutions, we want to hear from you. Elevate your career with us and be part of shaping the future! Job Description In your new role you will: Identify and understand the different needs and requirements of consumers and data providers (e.g. transaction processing, data ware housing, big data, AI/ML) and translate business digitalization needs to technical system requirements. Team up with our domain-, IT- and process experts to assess the status quo, to capture the full value of our data and to derive target data-ecosystems based on business needs Design, build, deploy and maintain scalable and reliable data assets, pipelines and architectures. Team-up with domain IT- and process experts and especially with you key users to validate the effectiveness and efficiency of the designed data solutions and contribute to their continuous improvement and to their future-proofing. Support data governance (Data Catalogue, Data Lineage, Meta Data, Data Quality, Roles and Responsibilities) and enable analytics use cases with a focus on data harmonization, connection and visualization. Drive and/or contribute to digitalization projects in cross-functional coordination with IT and business counterparts (e.g. data scientists, domain experts, process owners). Act as first point of contact for data solutions in the ATV QM organization to consult and guide stakeholders to leverage the full value from data and to cascade knowledge of industry trends and technology roadmaps for the major market players (guidelines,principles, frameworks, industry standards and best practice, upcoming innovation, new features and technologies) Your Profile You are best equipped for this task if you have: A degree in Information Technology, Business Informatics, Computer Science or related field of studies. At least 5 years of relevant work experience related to Data Engineering and/or Analytics with strong data engineering focus Ability to translate complex business needs into concrete actions Excellent expertise of database concepts (e.g. DWH, Hadoop/Big Data, OLAP), related query languages (e.g. SQL, Scala, Java, MDX) Expertise in data virtualization (e.g. Denodo) Working knowledge on the latest toolsets for data analytics, reporting and data visualization (e.g. Tableau, SAP BO) as well as in Python, R and Spark is a plus Ability to work both independently and within a team We are on a journey to create the best Infineon for everyone.

1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness andparasitic optimisations 3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. 4. Participate in building and enhancing layout flow for faster, higher quality design process. 5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks 6. Collaborate with Circuit Designers to solve challenging problems 7. Writing /PYTHON scripts to automate repetitive tasks 8. Work with Place and Route engineer to integrate custom macros into top level. 9. Able to perform design reviews across global team 10. Work closely with required global teams to ensure the success of the whole product. 11. Leadership in delivery of macros we plan to own from India Job requirements: 1. Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers etc. 2. Experience in designing layouts for high-speed circuits is a plus. 3. Layout experience in the following technology nodes3nm, 5nm and 7nm FinFET. 4. Good team worker with multi-discipline, multi-cultural and multi-site environments 5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms 6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions7. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise The Analog layout design engineer with experience in next generation Ultra high speed serial IO link (HSS) interface for Cognitive, ML,DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high speed 32G/50G/112G IO link interfaces. Preferred technical and professional experience Experience in 7 and 14 nm analog layout design. Working on Cutting edge technology and HSS domain . Quick learner, deep layout design knowledge, problem solving skills and good communication skills with cross teams across the Geos.

About Marvell . Your Team, Your Impact This position is with ASIC design physical implementation (PD) team part of Central Engineering business unit at Marvell, Bangalore. This team as part of global Implementation team plays a key role in Netlist to GDS implementation, covering Synthesis, P&R, Timing, PV and Power implementation all custom ASICs for all the OEM s. We are looking for individuals with the domain of physical design having Block /Subsystem level implementation experience on hierarchical designs using industry standard tools. What You Can Expect Work with a global team on the physical design of complex chips at Block/Partition/Full-Chip level. You will also play a critical role in refining the methodology to enable an efficient and robust design process working closely with the methodology team. Your tasks will include performing synthesis, place and route, as well as timing analysis and closure on a given hierarchical design at block/partition/full-chip level. You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues. Collaboration with the frontend team will be crucial to ensure successful tapeouts. Additionally, your involvement with the global timing team will include debugging and resolving any block/partition level timing issues encountered at the Chip level. This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell. What Were Looking For Have completed a Bachelor s OR a Masters Degree in Electronics/Electrical/VLSI field and have atleast 10+ years of related professional experience in physical design at Partition/Subsystem/Chip level with a proven track record of successful tape-outs. In your coursework, you must have completed a course in digital electronics, CMOS design and projects that involved circuit design & analysis. Good understanding of standard RTL to GDS flows and methodology, experience in designing ICs at advanced technology nodes (e. g. , 7nm, 5nm, or below) is highly desirable. Working knowledge on any of the scripting in languages such as Perl, tcl, AWK and Python. Knowledge of Verilog/VHDL basics is an added advantage. Good communication skills and self-discipline contributing in a team environment. In-depth knowledge and hands-on experience with industry-standard physical design tools and methodologies, including synthesis, floor planning, placement, clock tree synthesis, routing, and physical verification. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-KP1

Drive local sales initiatives and develop strong customer relationships in the semiconductor industry. Promote and sell a broad range of electronic and industrial automation components. Possess technical knowledge of: Electronic Components: IGBTs, MOSFETs, Diodes, Capacitors, Terminal Blocks/Connectors, Semiconductors Automation Products: Drives, Sensors, PLCs, Encoders, Limit Switches, Vision Systems Demonstrated experience in B2B technical sales, preferably in the semiconductor and industrial sectors. Solid understanding of electronic components and automation systems. Pls Contact: 9810420476 Send your resume to venuspc9@gmail.com and venuspchr@gmail.com

Develop a growth strategy focused both on financial gain and customer satisfaction, Keep records of sales, revenue, invoices etc. Visiting clients Pan India, experience electronic components & semiconductor industry.

Taking charge of all internal and external communications in India, this role embodies the spirit of strategic planning and creativity in managing media relations, social media, corporate brand marketing, event management, and internal communications. It supports our senior executives while fostering close collaboration with Sales Marketing in India. By engaging with local stakeholders - media, associations, and authorities - we can inspire effective communication that resonates with our diverse audiences, including employees, the media and customers. Job Description Develop and implement yearly communication plans , aligning global strategies with local market needs and Infineons Employer Value Proposition. Provide executive communications support to the Managing Director India and selected C-Level leaders. Build, enforce and maintain relationships with local key media (Corporate and trade media), adapting and distributing press releases, and pitching stories to secure media coverage. Act as a company spokesperson and support global media initiatives/briefings. Develop strategic concepts for trade fairs/events, including umbrella themes, storylines, core messages, content ideas, formats, and speakers tailored to specific target groups. Implement events as a holistic cross-channel communication approach, collaborating with internal teams (Brand Marketing, Corporate Communications, Public Policy) and external partners to deliver high-quality brand experiences and wide reach. Adapt global marketing campaigns to local market needs by identifying key topics and ensuring omnichannel distribution. Continuously track campaign performance to optimize results. Oversee Corporate events in India (eg internal external events, signature events) , in close collaboration with Corporate Communications, Brand Marketing and Live Communications teams. Leverage digital channels, including social media and content marketing, to analyze trends and drive targeted communication. Establish a new social media team member to steer local social media presence (Corporate content and paid campaigns), aligning with global and local topics, and collaborating with Corporate Communications and Brand Marketing teams. Drive internal communications activities with focus on regional needs to engage, inform, and inspire our employees; plan and implement local internal communication activities as we'll as adapt global people and transformation projects for local use in close alignment with Corporate Communications. Be responsible for the regionally allocated budget (from local and global). Define clear KPIs to make goals and value contribution visible and results quantifiable wherever possible and linked to the entire customer journey. You are best equipped for this task if you have: Minimum of 5 years leadership experience in integrated, wholistic communications functions. Experience in international organizations. Strong network in India. Leadership and project management skills. Stress resistant and collaborative.

The Data Engineer will serve as a technical expert in the fields ofdesign and develop AI data pipelines to manage both large unstructuredand structured datasets, with a focus on building data pipelines for enterprise AI solutions Job Description Working closely with data scientists and domain experts to design anddevelop AI data pipelines using agile development process. Developing pipelines for ingesting and processing large unstructuredand structured datasets from a variety of sources, with a specificemphasis on creating solutions for AI solutions to ensure efficient andeffective data processing. Work efficiently with structured and unstructured data sources. Work with cloud technologies such as AWS to design and implement scalable data architectures Supporting the operation of the data pipelines involves troubleshooting and bug fixing, as we'll as implementing change requeststo ensure that the data pipelines continue to meet user requirements. Your Profile Masters or bachelors Degree in Computer Science/Mathematics/Statistics or equivalent. Minimum of 3 years of relevant work experience in data engineering Extensive hands-on experience in conceptualizing, designing, andimplementing data pipelines. Proficiency in handling structured dataOracle unstructured data formats (eg, PPT, PDF, Docx), databases(RDMS, Oracle/PL SQL, MySQL, NoSQL such as Elasticsearch, MongoDB,Neo4j, CEPH) and familiarity with big data platforms (HDFS, Spark,Impala). Experience in working with AWS technologies focussing on buildingscalable data pipelines. Strong background in Software Engineering Development cycles(CI/CD) with proficiency in scripting languages, particularly Python. Good understanding and experience with Kubernetes / OpenshiftPlatform. Front-end Reporting Dashboard and Data Exploration tools -Tableau Good understanding of data management, data governance, and datasecurity practices. Highly motivated, structured and methodical with high degree ofself-initiative Team player with good cross-cultural skills to work in internationalteam Customer and Result orientated

The AI Engineer will serve as a technical expert in the fields of AIML,NLP, LLM deeper understanding and experience in Software Engineering. Job Description Work as a technical expert with extensive knowledge in TraditionalAIML, DL, NLP, LLM RAG, Chatbot and other AI areas. Utilizingstatistical analysis, machine learning, and data visualizationtechniques to extract insights from large datasets Transforming prototypes into production solutions with best practicesfor both development and deployment. Developing and maintaining software applications, dashboards andsystems that incorporate AI and machine learning components Focus on AI Solution scalability, efficiency, and real-timeprocessing, while maintaining the integrity of the underlying datascience principles Supporting the operation of the solutions involves troubleshootingand bug fixing, as we'll as implementing change requests to ensure thatthe solutions continue to meet user requirements. Monitor and analyse AI system performance, identifying areas forimprovement and optimization. Be involved in AI infrastructure maintenance supporting userqueries related to the AI tools You are best equipped for this task if you have: Masters or bachelors Degree in Computer Science/InformationTechnology or equivalent. Minimum of 3 years of relevant work experience in NLP/AI/ML ,including at least 1 year focusing on LLM. Experience in Software Engineering Development cycles ( CI/CD) withproficiency in scripting languages, particularly Python. Good understanding and experience of Kubernetes / Openshift Platform. Good understanding of RESTful architecture and API development bestpractices. Familiarity with Agile development methodologies, such as Scrum orKanban. Basic web development knowledge would be beneficial, but notessential. Highly motivated, structured and methodical with high degree ofself-initiative Team player with good cross-cultural skills to work in internationalteam Customer and result orientated

You are an expert in digital and social media and enthusiastic about technology You like to approach social media campaigns holistically and know that powerful content is only the beginning This new role is a key part of bringing our corporate and local messages, brand stories and campaigns to life. Infineon is looking for a passionate individual to evolve this role, drive effective social media and digital messaging. As part of the Corporate Communications team in India you will work cross-functionally and support a strategic approach in recommending the optimal messaging and digital assets and executing the plan through our regional and global social media channels. Job Description Implement and drive communication concepts and campaigns on social media and in the digital area in India in close collaboration with the Corporate and Marketing Communications teams. Take over the (paid and organic) content management from the idea to the playout, manage and optimize social media messages and campaigns working closely with the Corporate Marketing Communications teams, and other relevant stakeholders (eg Managing Director) to jointly develop and execute an overall social media strategy. Identify relevant stories that prove our corporate brand messages and develop creative state-of-the-art social media formats for it, adhering to Infineon s brand guidelines; responsible for publishing the final content on the platforms. Analyze digital and social media key figures, create reports and derive learnings from them. Assist in budget allocation, paid media cadence and timing to execute the strategy. Ensure that campaigns and projects are developed and successfully completed on time. You are best equipped for this task if you have: A degree in ( digital) marketing , communications , economics , or related field. 1-2 years of experience in digital and social media incl. content planning on several channels, creative organic storytelling, and paid advertising as we'll as performance monitoring. Experience creating content , both written and digital (images, photos, videos, etc) Knowledge of current social media landscape , different channels, content features. Excellent communication skills - verbal and written - comfortable in a team environment. Very good knowledge of the English language , both written and spoken. Exceptional ability to work cross-functionally and collaboratively.

The software engineer will serve as a technical expert in the fields ofdesign, develop and deploying scalable and secure applications thatsupport our AI and machine learning initiatives. Job Description Working closely with data scientists, data engineers, applicationowners and domain experts to design and develop software applicationsusing agile development process. Design, develop, and deploy full stack web applications using a rangeof technologies, including state-of-the-art front-end frameworks,back-end frameworks and databases (relational and NoSQL). Design and develop high-performance APIs for AI services capable of handling a large volume of concurrent requests Work with cloud technologies such as AWS to design and implement scalable data architectures Supporting change management and operations, optimizing and improvingexisting applications. You are best equipped for this task if you have: Masters or bachelors Degree in Computer Science/ InformationTechnology or equivalent. Minimum of 3 years of relevant work experience in software development Extensive hands-on experience in frontend frameworks such as Vie.js/react.js , backend frameworks such as Node.js/Django/Flask Experience in working with AWS technologies focussing on applicationbuilding Strong background in Software Engineering Development cycles( CI/CD) with proficiency in scripting languages, particularly Python. Good understanding and experience with Kubernetes / OpenshiftPlatform. Experience with authentication and authorization mechanisms (eg, OAuth 2.0, JWT ). Strong understanding of concurrency, parallelism, synchronization,and thread safety in Python . Front-end Reporting Dashboard and Data Exploration tools -Tableau Exposure to key AI technologies and algorithms such as LLM, ClassicalML, NLP, etc is an advantage. Highly motivated, structured and methodical with high degree of self-initiative Team player with good cross-cultural skills to work in internationa lteam Customer and Result orientated.

Complexity in consumer systems is growing exponentially. ADI is well positioned to leverage its core sensor and signal processing technology to solve these complex problems. We are looking for an energetic Staff Test Engineer who can ensure product quality and functionality using advanced testing methodologies and test strategies. The candidate: Should be able to create system-level test strategies and design and develop system-level test plans across multiple subsystems to ensure software functionality and quality while adhering to requirements and company standards. Must possess the ability to design and develop test automation frameworks, execute both manual and automated tests, analyze the results, and identify as well as document defects. Should be able to collaborate with software architects and developers to understand product design and provide input on software testing requirements and performance expectations. Should be able to lead the integration testing, mentor junior engineers, and create, adhere to, and promote best test engineering practices. Should be able to evaluate new testing technologies and tools and propose processes to enhance the product quality. Primary Qualifications: BS or MS in Electrical or Computer Engineering or related field 8+ years of Industrial experience in the Test suite design, development Strong experience with system level tests on multi-core environments Strong experience with integrating, building, and testing of multi-threaded applications. Strong Python and C/C++ programming skills Experience with embedded real-time operating systems Experience with SCM tools (GIT, SVN, Clearcase, Perforce, etc.) Experience with defect tracking tools (Jira, Bugzilla, etc.) Working knowledge of digital signal processing (DSP) and algorithm testing experience Experience with machine learning, deep neural network technologies, PyTorch, TensorFlow platforms Secondary Qualifications: Strong working knowledge of a software development process (e.g., Agile, Waterfall) Conceptual understanding on Object-Oriented concepts and methodologies Strong system-level knowledge in audio, video and TWS domains

locationsIndia, Bangalore time typeFull time posted onPosted 6 Days Ago job requisition idJR0274955 Job Details: About The Role : Foundry Services (FS) is an independent foundry business that is established to meet our customers' unique product needs. With the first Open System Foundry model in the world, our combined offerings of wafer fabrication, advanced process, and packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities help our customers build their innovative silicon designs and deliver full end-to-end customizable products from Intel's secure, resilient, and sustainable source of supply. This job opportunity in FS will be part of the Customer Solutions Engineering (CSE) group which is responsible for the portions of the system foundry that brings the best of Intel technologies to FS customers, differentiating and accelerating their solutions from architecture to post-silicon validation. The role of a Design Verification Lead includes but is not limited to UVM based testbench development at Subsystem, SOC level and BFM integration. Creating test plans for RTL validation including functional coverage and assertions Developing pre-Silicon functional validation tests and testbench components like monitors and scoreboards Bring up and debug UPF based and Gate level and performance simulations Working on core based simulations and C testcases, handshake between SV and C tests. Hands on experience in Highspeed protocols like PCIE and UCIE Working with ARM architecture and protocols like AXI, APB, CHI, CXS. Mentoring and coaching team members Qualifications: Masters / Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or in a related field of study 10+ years of experience in Design Verification Developing UVM and/or Formal-based verification architectures and methodologies Preferred Qualifications: Graduate/post-graduate degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field of study Experience in DV and testbench development at Subsystem and SOC level. Experience with scripting languages Low power simulations experience (e.g., UPF) Formal verification experience Experience with PCIE, UCIE, DDR and ARM Architecture Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: Intel Foundry is dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. As stewards of Moore's Law, we innovate and foster collaboration within an extensive partner ecosystem to advance technologies and enable our customers to design leadership products. Our strategic investments in geographically diverse manufacturing capacities bolster the resilience of the semiconductor supply chain. Leveraging our technological prowess, expansive manufacturing scale, and a more sustainable supply chain, Intel Foundry empowers the world to deliver essential computing, server, mobile, networking, and automotive systems for the AI era. This position is part of the Foundry Services business unit within Intel Foundry, a customer-oriented service organization that is dedicated to the success of its customers with full P&L responsibilities. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

locationsIndia, Bangalore time typeFull time posted onPosted 5 Days Ago job requisition idJR0273873 Job Details: About The Role : Dry Etch group under Intel's Technology Development organization is seeking a skilled and motivated process engineer with emphasis on data analysis to support semiconductor manufacturing research and development processes for our U.S.-based operations. The ideal candidate will have a strong background in data analytics, a solid understanding of semiconductor manufacturing, and the ability to work collaboratively across time zones. This position requires advanced problem-solving skills, technical expertise, and experience in data-driven decision-making to optimize manufacturing performance. Key Responsibilities: Analyze manufacturing process data to identify trends, anomalies, and improvement opportunities. Develop dashboards and reports for real-time monitoring and decision-making support for U.S.-based teams. Collaborate with U.S. semiconductor manufacturing teams to understand process requirements and implement data solutions. Utilize advanced statistical methods, machine learning, and predictive modeling to enhance yield, reduce defects, and optimize production. Ensure data integrity, accuracy, and security in all analyses and reporting. Support root cause analysis for process issues using data-driven methodologies. Maintain and improve data pipelines for automated data processing and reporting. Coordinate with cross-functional teams (engineering, operations, and IT) to deliver. Qualifications: Minimum Qualifications Masters degree or Bachelors in electrical engineering, Computer Science, Mechanical Engineering, Chemical Engineering, Computer Engineering, Applied Mathematics, or other relevant related degrees with Industry experience in one of the following: B.Tech with 5+ years and M.Tech with 2+ years of experience in data analytics, preferably in a manufacturing or semiconductor environment. Strong understanding of statistical analysis, machine learning models, and process control methodologies. Preferred Qualifications: Proficiency in data analysis tools and programming languagesPython, R, SQL, etc. Experience with visualization tools such as Tableau, Power BI, or equivalent. Knowledge of semiconductor manufacturing processes and yield analysis is highly preferred. Excellent problem-solving and analytical skills with a keen eye for detail. Strong communication and collaboration skills to work with global teams. Ability to manage multiple priorities in a fast-paced environment. Working Hours: The position will primarily align with local time, with some flexibility to accommodate collaboration across U.S. time zones. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in theTechnology Development and Manufacturing Groupare part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; - Grade Specific Focus on Electrical, Electronics Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers. Skills (competencies)

About Marvell . Your Team, Your Impact Built on decades of expertise and execution, Marvell s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, data center, and networking applications. What You Can Expect As a Senior Staff Physical Design Engineer (PnR), you will be part of our Implementation team and responsible for running/supporting/maintaining the PnR Flow using industry standard EDA tools for designing the next generation Multi-Ghz high-performance ASIC chips in leading-edge CMOS process technology. Work with design teams across various disciplines such as Digital/RTL/Analog in helping them take their blocks (custom, PnR) through the physical design flow and making sure all the blocks meet timing requirements. Implement/Support blocks with multi-voltage designs through all aspects of RTL to GDS Implementation (Place and Route, static timing, physical verification) using industry standard EDA tools. Work with physical verification team in integrating these blocks seamlessly into full chip partitions. Have a good understanding of global integration and full chip physical verification. Provide technical direction, coaching, and mentoring to employees on the team and others when necessary to achieve successful project outcomes. Writing scripts in TCL and Perl to achieve productivity enhancements through automation is required. HandsOn experience with Bump planning and routing is required. Hands on experience and a solid understanding in all of the following physical design flows and methodologies: Synthesis/PnR, power/EM/IR analysis, power intent (UPF/CLP). What Were Looking For BSEE or MS with 9+ years of experience running an industry standard EDA tool for PnR signoff. Understanding of several timing-related concepts is required: setup, hold, clocking, timing corners, timing constraints, noise, and process variation . Experience in tape-outs of high performance SOC is required. Physical design knowledge, from netlist handoff to GDS tape out including floor planning, place and route, clock tree synthesis, timing closure and physical verification. Work with logic verification, and design teams to understand and implement the design requirements for clocking and power management. Knowledge of scripting languages such as Perl/TCL is required. Diligent, detail-oriented, and should be able handle delegation of assignments efficiently. Must possess effective communication skills, self-driven individual and a good team player. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-MN1

About Marvell . Your Team, Your Impact As member of the physical design team at Marvell you will have the opportunity to work on digital design for ASICs, Physical Implementation, Power Supply integrity checks Low Power design Signoff. Opportunity to work for complete SoC design cycle of ASICs, starting from Architecture definition, feasibility planning/benchmarking for Power/Performance/Area/Yield to end-to-end design/Implementation/Signoff. Opportunity to work on challenging design architecture across Networking, Processor, Computing, automotive, Connectivity and Security, in the technology nodes across 3nm/5nm/7nm and more. What You Can Expect As a Principal Physical Design Engineer (PnR), you will be part of our Implementation team and responsible for running/supporting/maintaining the PnR Flow using industry standard EDA tools for designing the next generation Multi-Ghz high-performance ASIC chips in leading-edge CMOS process technology. Work with design teams across various disciplines such as Digital/RTL/Analog in helping them take their blocks (custom, PnR) through the physical design flow and making sure all the blocks meet timing requirements. Implement/Support blocks with multi-voltage designs through all aspects of RTL to GDS Implementation (Place and Route, static timing, physical verification) using industry standard EDA tools. Work with physical verification team in integrating these blocks seamlessly into full chip partitions. Have a good understanding of global integration and full chip physical verification. Provide technical direction, coaching, and mentoring to employees on the team and others when necessary to achieve successful project outcomes. Writing scripts in TCL and Perl to achieve productivity enhancements through automation is required. HandsOn experience with Bump planning and routing is required. Hands on experience and a solid understanding in all of the following physical design flows and methodologies: Synthesis/PnR, power/EM/IR analysis, power intent (UPF/CLP). What Were Looking For BSEE or MS with 12+ years of experience running industry standard EDA tools for PnR signoff. Understanding of several timing-related concepts is required: setup, hold, clocking, timing corners, timing constraints, noise, and process variation Experience in tape-outs of high performance SOC is required. Physical design knowledge, from netlist handoff to GDS tape out including floor planning, place and route, clock tree synthesis, timing closure and physical verification. Work with logic verification, and design teams to understand and implement the design requirements for clocking and power management. Knowledge of scripting languages such as Perl/TCL is required. Diligent, detail-oriented, and should be able handle delegation of assignments efficiently. Must possess effective communication skills, self-driven individual and a good team player. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-MN1

Job Title: Front-End Program Manager Location: Bangalore, India Experience: Minimum 10 years Job Description: We are seeking an experienced Front-End Program Manager to lead and coordinate server platform and system engineering projects. This role involves managing the development, build, and validation of systems supporting bring-up and validation activities for our Server and Datacenter Business Unit. Key Responsibilities: Develop detailed plans and drive schedules for platform/system design, build, and test activities. Collaborate with cross-functional teams to ensure alignment of technical requirements and deliverables. Identify and actively manage program risks and dependencies. Manage the creation of system BOMs and drive platform build logistics, including critical components and costing. Collect team status and report on design and development activities versus planned targets throughout the project lifecycle. Requirements: 15+ years of experience in the high-tech industry, with a minimum of 10 years in Technical Program Management focusing on hardware development. Proven ability to drive technical discussions and understand the impact on program deliverables. Experience managing diverse cross-functional teams across geographies, including hardware teams. Excellent communication skills, both written and verbal. Strong reporting skills with keen attention to detail. Experience in platform design, build, and validation. Strong understanding of program management methodologies such as Agile, Scrum, and Waterfall. Experience managing hardware development projects using Agile methodologies is a plus. Proficiency in MS Office, MS Project, Confluence, MS SharePoint, and JIRA. Proven ability to manage multiple complex projects simultaneously. How to Apply: Interested candidates can apply through Naukri.com or send their resumes to swarnamanjari@mirafra.com

Bachelor's degree in Engineering, Computer Science, or related field. 4+ years of Program Management or related work experience. 3+ years of working with operating budgets, resources, and/or project financials. Successful candidate will be part of the GOSC Infra HW Program Management team, providing full line of solutions to the Snapdragon family of products and will be primary responsible for program execution of complex semiconductor devices in terms of schedule, performance, power, and cost. Lead, drive and influence execution of complex programs throughout lifecycle to meet plan of records and ensure successful and timely delivery of a quality product. Organize and lead cross-functional teams to develop project schedules, resource plan, metrics, and overall project plans of records. Determine risks, develop mitigation strategies, and communicate information to internal and external key stakeholders. Troubleshoot program issues and helps to develop alternative program tasks, schedules, milestones, resource plans, processes etc. to resolve program issues and conflicts. Roll-up and reporting regularly to senior management on key product development milestones, metrics, risk mitigation plans and staffing status. Participate in functional team reviews and coordinate or assure compliance to department checklists and procedures. Ensures change control, development reviews, and other product development processes are effectively implemented. Take active role in innovating and improving the current program management metrics and processes. Lead the development of processes and metrics by driving implementation of best project management practices to optimize team execution and deliverables quality. Lead teams through the development process with attention to cultural priorities: collaboration, partnering, can do attitude. Must be articulate, have a leadership presence, and be able to develop top quality presentations that are concise and engaging. Must be able to multi-task and react to changing business needs with clear direction for subsequent action plans. Minimum Qualifications: Develops, defines, and executes plans of record, including, schedules, budgets, resources, deliverables, and risks. Monitors and drives the program from initiation through delivery, interfacing with internal and external stakeholders across functions on technical matters, as needed. Monitors on-time delivery, and achievement of program milestones. Represents the program and drives alignment across stakeholders. Principal Duties & Responsibilities Collaborates with key stakeholders and program sponsors to develop goals, set the prioritization of deliverables, and discuss necessary priorities and stakeholder needs. Manages and takes responsibility for multiple small programs/technology with moderate complexity or a single complex program/technology by applying up-to-date program management knowledge to meet deadlines. Develops and manages the execution of the program Plan of Record (e.g., on time, on budget, within scope) for multiple small programs or a single medium sized or complex programs/technologies which includes schedule and resource forecasting, stakeholder identification, method and frequency of communication, scope, and prioritization. Tracks and manages all key metrics pertaining to a program and identifies when metrics deviate significantly from Plan of Record; escalates issues in a timely manner and proposes corrective actions. Manages and prioritizes the work of the program team by establishing schedules, task assignments, and tracking tasks of team members. Identifies program issues/risks and creates a risk mitigation plan for multiple small programs or a single medium sized or complex program. Maintains and updates the risk tracker. Helps to promote program vision and objectives within own team, and ensures program objectives are met or exceeded. Supports the adoption of processes by applying best practices and identifying and recommending process improvement opportunities within respective programs. The Responsibilities Of This Role Include Working independently with little supervision. Using verbal and written communication skills to convey complex and/or detailed information to multiple individuals/audiences with differing knowledge levels. May require strong negotiation and influence, communication to large groups or high-level constituents. Having a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to provide input on key decisions). Completing tasks that do not have defined steps; simultaneous use of multiple mental abilities is generally required to determine the best approach; mistakes may result in significant rework. Exercising substantial creativity to innovate new processes, procedures, or work products within guidelines or to achieve established objectives. Using deductive and inductive problem solving; multiple approaches may be taken/necessary to solve the problem; advanced data analysis and interpretation skills are required. Occasionally participates in strategic planning within own area affecting immediate operations. Minimum Qualifications Bachelors degree in Computer Engineering, Electrical Engineering or equivalent combination of technical education and work experience Overall 10+ yrs of Semiconductor Industry experience and minimum 3+ years of experience in a technical project management role Must be experienced in complete ASIC lifecycle development including pre-silicon, silicon validation and IP development process Must have strong interpersonal skills and be able to effectively communicate at all levels Experience with Waterfall and Agile project management methodologies Experience with project schedule and resource management tools, advanced Excel, power-point. Preferred Qualifications Masters degree in Computer Engineering, Electrical Engineering or equivalent combination of technical education and work experience Experience in managing global programs/teams across different time zones Experience with Atlassian tools (JIRA, Confluence) Ability to learn and adapt quickly Detail and action oriented, self-starter, leader and motivator Educational Requirements Required: Bachelor's, Computer Engineering and/or Computer Science and/or Electrical Engineering Preferred: Master's, Computer Engineering and/or Computer Science and/or Electrical Engineering

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. We are seeking a dedicated and skilled EM/IR Methodology Engineer to join our team. The role involves developing and maintaining methodologies for Electromigration (EM) and Voltage Drop (IR) analysis to ensure robust and reliable designs in advanced semiconductor technologies. The ideal candidate will work closely with cross-functional teams to optimize power delivery networks and ensure design compliance with EM/IR standards. Key Responsibilities: Develop, validate, and optimize methodologies for Electromigration (EM) and Voltage Drop (IR) analysis for advanced semiconductor designs. Collaborate with design, CAD, and physical implementation teams to optimize power delivery networks. Enhance and automate workflows to improve PDN analysis efficiency. Partner with EDA tool vendors to enhance and customize EM/IR analysis tools. Support design teams in EM/IR verification and sign-off. Required Skills and Qualifications: Bachelors or Masters degree in Electronics, Electrical Engineering, or a related field. 3-5 years of experience in EM/IR analysis or physical design methodology. Strong understanding of Electromigration (EM) and Voltage Drop (IR) concepts and their impact on circuit reliability. Hands-on experience with EM/IR analysis tools such as Voltus , RedHawk , Totem , or equivalent. Preferable if worked on 2.5D/3D-IC , CoWoS technologies. Exposure to AI/ML concepts will be bonus. Proficiency in scripting languages such as Python , Perl , or Tcl to automate workflows. Good understanding of STA concepts. Strong problem-solving and analytical skills. Excellent communication and teamwork skills.

Job Description: We are seeking an experienced Bluetooth Low Energy ( BT/ BLE Stack Developer )to join our embedded systems team. The ideal candidate will have a strong background in BLE protocol stack development, embedded systems, and real-time operating systems (RTOS), particularly FreeRTOS. You will play a key role in designing, implementing, and maintaining Bluetooth communication layers for next-generation connected devices. Responsibilities: Design, develop, and maintain custom Bluetooth Low Energy (BLE) stacks and profiles. Work on BLE protocol layers (L2CAP, ATT, GATT, GAP, HCI) and application-level integration. Implement and optimize BLE features in embedded platforms running FreeRTOS. Debug and resolve complex issues related to Bluetooth communication, interoperability, and performance. Collaborate with hardware, firmware, and mobile application teams to ensure seamless integration. Maintain and enhance existing codebases written in C and C++. Conduct code reviews, write technical documentation, and mentor junior engineers. Requirements: 5+ years of hands-on experience in Bluetooth Low Energy (BLE) stack development. Strong programming skills in C and C++ . Solid understanding of Bluetooth protocol layers and BLE architecture. Experience with FreeRTOS or similar embedded RTOS environments. Familiarity with embedded development toolchains (ARM, GCC, IAR, Keil, etc.). Experience with power optimization techniques in low-power wireless communication systems. Knowledge of security protocols and pairing mechanisms in BLE. Preferred Qualifications: Knowledge of other wireless protocols (e.g., Zigbee, Thread, Wi-Fi). Familiarity with mobile app BLE integration (iOS/Android). Bachelors or Master’s degree in Electrical Engineering, Computer Engineering, or related field.

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures todays innovators stay Ahead of Whats Possible . Learn more at www.analog.com and on LinkedIn and Twitter (X) . AMS Verification Lead - Isolation group Analog Devices is seeking an experienced Analog Mixed Signal Verification engineer to join its Interface Isolation group based at its Bangalore Research Development offices in India. The group is the market leader in galvanic safety isolation products due to its proprietary iCoupler transformers and More Than Moore wafer fabrication technologies. As these technology capabilities advance there is an emerging need for greater complexity in the digital and mixed signal verification requirements to bring next generation ground-breaking products to the Medical, Industrial and Test Measurement markets. Role Lead the AMS verification effort of devices Contribute towards verification strategy and methodology improvement Understand device requirements and come up with traceable AMS verification plan Hands on contribution to AMS top level verification effort Lead a team of AMS engineers/contractors Code/generate SVRNM models of required analog blocks and validate against schematic. Develop directed tests in AMS environment or reuse constrained random UVM testcases Interface with global design teams through various phases of verification File and track bugs to closure in Jira Document results of assigned blocks and review the results with the team Requirements Bachelor of Engineering degree in electrical/electronic engineering or comparable degree 8+ years experience in chip level AMS (analog mixed signal) verification of SOC Familiarity with latest digital verification methodologies like digital mixed signal verification(DMS) using UVM Experience with mixed signal simulators such as Cadence AMS or equivalent Experience in running GLS and scan sims from top level Experience with SVRNM or verilogams behavioural model coding for analog blocks Team player with good analyzing and debugging skills Open to adopting new tools and flows Must have good verbal and written communication skills to work effectively with teams spread geographically