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Design Engineering Professional Acesoft Labs

3.0 - 6.0 years

5 - 8 Lacs

hyderabad

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Role & responsibilities Hands-on experience in developing/understanding building block schematics, memory schematics, running circuit simulation with spice simulators, DC analysis, transient analysis. Experience in deciphering circuit behavior from schematics. Familiarity with circuit characterization, timing libraries - files and formats, timing arcs Experience in Verilog MOS switch level models and netlist simulation with zero delay, unit delay, and path delay simulations. Familiarity with static timing analysis Hands-on experience in Gate level simulations with SDF back annotation. Debug SDF annotation issues and ensure good annotation coverage. Hands-on experience with latch based design...

Posted 2 months ago

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