Synthesis/STA Engineer (Applications Engineering) Synopsys

4.0 - 9.0 years

4 - 9 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

Desired Skills and Experience: Proficiency with STA, SDC. Proficiency with RTL, System Verilog. Strong understanding of front-end EDA design methodologies. Strong Perl, Tcl or Python scripting skills. Prior experience with logic synthesis tools is required. Prior experience using or supporting SDC tools would be a significant plus. Prior experience with RTL simulation, SVA would be a plus. Prior experience supporting front-end EDA tools would be a plus. Sound communication skills, verbal and written. Ability to produce product requirement documents. BS EE/CE. 4 years experience with STA/Synthesis.

Posted 5 months ago

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Principal Applications Engineer STA Synopsys

10.0 - 15.0 years

5 - 7 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

What You ll Need: Proficiency with STA, SDC. Proficiency with RTL, System Verilog. Strong understanding of front-end EDA design methodologies. Strong Perl, Tcl, or Python scripting skills. Prior experience with logic synthesis tools. Prior experience using or supporting SDC tools (a significant plus). Prior experience with RTL simulation and SVA (a plus). Sound communication skills, both verbal and written. Ability to produce detailed product requirement documents. BS in Electrical or Computer Engineering with 10+ years of experience in STA/Synthesis/Front-End Flows.

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Quest Global Hiring RTL Design For Bangalore Quest Global

7.0 - 12.0 years

35 - 65 Lacs

Hyderabad, Bengaluru

Work from Office

Greetings from Quest Global Please find the details and kindly send me your Profile . RTL Design 10-15 Years Location : Bangalore/Hyderabad 1. Should have worked on ASIC/SOC projects using 22nm or smaller technology node 2. Expertise in automated RTL Integration using any of the industry standard tool/EDA flow 3. Expertise in SDC and UPF constraints development and checking 4. Expertise in Timing violation debug/fix at netlist level 5. Good knowledge on AHB/AXI/APB/PIPE interface 6. Expertise in Lint, CDC and VCLP, Synthesis, LEC 7. Very Strong in Python and TCL scripting • Nice to have skills: 8. Exposure to PCIe/Ucie 9. Experience in Leading small rtl design team • Location: Bangalore and ...

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STA lead Xanika Infotech

8.0 - 11.0 years

25 - 30 Lacs

bengaluru

Work from Office

Role & responsibilities We are seeking an experienced Full-Chip STA Engineer to drive timing closure and sign-off across the entire SoC/ASIC design. The role requires expertise in multi-block integration, multi-mode/multi-corner analysis, and sign-off methodology for advanced technology nodes. Key Responsibilities: Perform full-chip static timing analysis for all functional and test modes across multiple PVT corners. Own SDC constraint generation, validation, and refinement at top-level. Collaborate with block-level STA, physical design, synthesis, and clock teams to achieve timing closure . Debug and resolve full-chip setup/hold violations through ECOs, floorplan changes, and clock optimiza...

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