2 Sdc Engineer Jobs

Join the dynamic front-end design team at Cisco Silicon One and be a part of the heart of silicon development. Engage in every facet of chip design, from architecture to validation, utilizing the latest silicon technologies to create groundbreaking devices. Cisco Silicon One empowers customers to deploy top-tier silicon across diverse applications, shaping revolutionary solutions by designing and testing advanced ASICs that integrate networking, compute, and storage into a single system. Gain exposure to all aspects of our systems with tightly integrated hardware and software solutions. We are looking for a talented ASIC engineer with a proven track record in high-performance products to make a significant impact in the industry. Join us and push the boundaries of what's possible! As a diligent Design/SDC Engineer, you will work with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Collaborate with Front-end and Back-end teams to refine design and timing constraints for seamless physical design closure. Contribute to developing next-generation networking chips by overseeing full-chip SDCs and working with physical design and DFT teams to close full-chip timing in multiple timing modes. You may also have the option to do block-level RTL design or block or top-level IP integration. Develop efficient methodologies to promote block-level SDCs to full-chip and ensure correctness and quality of SDCs early in the design cycle. Review block-level SDCs, mentor RTL design owners on SDC development, and create full-chip clocking diagrams and related documentation. Minimum Qualifications: - Bachelor's Degree in Electrical or Computer Engineering with 7+ years of ASIC or related experience or Master's Degree in Electrical or Computer Engineering with 5+ years of ASIC or related experience - Experience with block/full chip SDC development in functional and test modes - Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus - Understanding of related digital design concepts (e.g., clocking and async boundaries) - Experience with synthesis tools (e.g., Synopsys DC/DCG/FC), Verilog/System Verilog programming Preferred Qualifications: - Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence) - Experience with Spyglass CDC and glitch analysis - Experience using Formal Verification: Synopsys Formality and Cadence LEC - Experience with scripting languages such as Python, Perl, or TCL Join Cisco, where every individual brings their unique skills and perspectives to power an inclusive future for all. Celebrate diversity, unlock potential, and experience continuous learning and development. Be a part of a community that fosters belonging, learns to be informed allies, and makes a difference through volunteer work. Cisco is the worldwide leader in technology that powers the internet, helping customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals. Take your next step towards a more inclusive future with us!,

Join our dynamic front-end design team at Cisco Silicon One, where innovation meets cutting-edge technology! As part of the heart of silicon development at Cisco, you'll engage in every facet of chip design, from architecture to validation, using the latest silicon technologies to create groundbreaking devices. Cisco Silicon One is the only unified silicon architecture that empowers customers to deploy top-tier silicon across diverse applications, from top-of-rack switches to expansive data centers. Be a part of shaping Cisco's revolutionary solutions by designing and testing advanced ASICs that integrate networking, compute, and storage into a single system. With tightly integrated hardware and software solutions, you'll gain exposure to all aspects of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready to make a significant impact in the industry. Join us and push the boundaries of what's possible! You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you'll contribute to developing next-generation networking chips. Responsibilities include: - Being a member of the design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. - Option to also do block-level RTL design or block or top-level IP integration. - Helping develop an efficient methodology to promote block-level SDCs to fullchip and to bring fullchip SDC changes back to the block level. - Helping develop and apply a methodology to ensure correctness and quality of SDCs as early as possible in the design cycle. - Reviewing block-level SDCs and clocking diagrams and mentoring other RTL design owners on SDC development. - Creating fullchip clocking diagrams and related documentation. Minimum Qualifications: - Bachelors Degree in Electrical or Computer Engineering with 7+ years of ASIC or related experience or Masters Degree in Electrical or Computer Engineering with 5+ years of ASIC or related experience. - Experience with block/full chip SDC development in functional and test modes. - Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus. - Understanding of related digital design concepts (e.g., clocking and async boundaries). - Experience with synthesis tools (e.g., Synopsys DC/DCG/FC), Verilog/System Verilog programming. Preferred Qualifications: - Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence). - Experience with Spyglass CDC and glitch analysis. - Experience using Formal Verification: Synopsys Formality and Cadence LEC. - Experience with scripting languages such as Python, Perl, or TCL. Join us at Cisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all. Our passion is connection, and we celebrate our employees" diverse set of backgrounds focusing on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best but be their best. We understand our outstanding opportunity to bring communities together, and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer 80 hours each year allows us to give back to causes we are passionate about, and nearly 86% do! Our purpose, driven by our people, is what makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. We ensure that every step we take is a step towards a more inclusive future for all. Take your next step and be you, with us!,