Design Testability Engineer Insightek Global Consulting

5.0 - 10.0 years

20 - 35 Lacs

bengaluru

Work from Office

Preferred candidate profile DFT Fundamentals including JTAG, Scan, ATPG, IEEE 1687 iJTAG, EDT Architecture Scan Insertion using Fusion Compiler or other EDA tools ATPG Coverage Analysis and DRC clean up ATPG patterns simulation and debug using SNPS VCS and Verdi tools Understanding of Design for Test methodologies and DFT experience (e.g. JTAG 1149.x, IEEE 1500, IEEE 1687 iJTAG, Scan, ATPG, Memory BIST, etc.) Familiar with DFT flow and EDA tools, including Fusion Compiler, Synopsys Tmax or Mentor Testkompress/Tessent, etc. Experienced with Verilog, System Verilog, VCS simulation tool, Perl/Shell scripting, and Verilog RTL design Experience in debugging Compressed ATPG patterns, MBIST, and JT...

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Senior Engineer Sivaltech

5.0 - 10.0 years

17 - 27 Lacs

bengaluru

Work from Office

Role & responsibilities • Hands-on experience in scan insertion, JTAG, ATPG DRC, and coverage analysis Proficiency in simulation debug with timing/SDF Experience with LBIST and Mixed Signal Radar ICs is highly desirable Ability to debug and root cause simulation failures Must be proactive, collaborative, and detail-oriented, capable of exercising independent judgment Preferred candidate profile Immediate joining

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Lead DFT Engineer Fiori Technology Solutions

10.0 - 12.0 years

20 - 25 Lacs

hyderabad, bengaluru

Work from Office

We are looking for a highly experienced DFT Lead Engineer to take ownership of Design-for-Test (DFT) architecture, implementation, and sign-off for complex flat SoC designs. This role requires deep expertise in PNR (Place-and-Route) within Cadence flow. Key Responsibilities Lead DFT strategy and implementation for flat SoC designs from RTL through tape-out. Develop and integrate test architectures including scan insertion, MBIST, LBIST, JTAG, and boundary scan. Work closely with the PNR team to ensure DFT structures are timing- and placement-aware. Drive test mode constraint creation and ensure compatibility with functional modes. Perform gate-level simulations for test logic verification. O...

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