51 Scan Insertion Jobs - Page 2

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 3+ years"™ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills

We are hiring DFT Engineer | Hyderabad Notice Period: 30 Days Position: DFT Engineer Looking for passionate professionals with 4 to 6 years of experience in Design for Test (DFT) to join our growing team in Hyderabad ! Key Responsibilities: Drive innovative DFT implementation at RTL and Gate level for SoC designs at both hard macro and chip top level, including: Scan insertion MBIST (Memory BIST) LBIST (Logic BIST) Boundary Scan Generate and validate ATPG patterns through simulation DFT verification using RTL and Gate-level simulations Collaborate with cross-functional teams across: Static Timing Analysis (STA) Synthesis Logic Equivalence Check (LEC) CLP Functional Verification & Validation Tool Proficiency: Experience with DFT tools from: Siemens Synopsys Cadence Technical Skills: Strong coding skills in: Verilog, VHDL C/C++ TCL, Perl, Python

ROLE & RESPONSIBILITIES: Incumbent will be responsible for Scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP Tests and Pattern validation w/wo Timing, DFT mode timing Analysis and sign off. Be responsible for a comprehensive DFT plan. Incumbent to work with DFT and cross functional teams. To architect and implement solutions for Scan and built-in self-test (Memory and Logic BIST) circuitry to test devices in the field. ESSENTIAL SKILLS & EXPERIENCE: Strong fundamentals on DFT and ASIC cycle. Sound expertise in Tcl, Perl, Shell scripting. Technically sound & good team player. Hands-on experience with DFT implementation using standard EDA and flow is a must. Experience on latest technology (28nm,16nm,7 nm) EDUCATION BACKGROUND: B.E./ B.S./ B.Tech/ M.S./ M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering.

The candidate should have skills and 5+ yrs in the field of scan and ATPG DFT knowledge with hands on experience. Scan extraction and DRC analysis along with Coverage debugs. ATPG experience and have to work on setup creation/pattern generations and debugs. Hands on Simulation experience with and without Timing. Post silicon debug support and scripting knowledge for day-to-day executions. I have to analyses the issues and need to react quickly with the team player's be a good Team player.

The candidate must have thorough knowledge of DFT basics such as DFT RTL insertion. scan insertion, fault models, ATPG, BIST techniques, and on-chip compression techniques that reduce test time and tester memory. Need to work with product engineering team for Silicon Bring-up and also support post-silicon debug. Interfacing with the design teams to ensure DFT design rules and guidelines are met Interact with PD and Front End Integration team for Scan Insertion Generating high quality manufacturing test patterns for stuck-at, transition fault models and CA model Simulating and verifying the ATPG and LBIST patterns Working with the product engineering teams on the delivery of manufacturing test patterns Developing, enhancing and maintaining scripts as necessary Able to technically guide and mentor junior folks in the team PREFERRED EXPERIENCE: Experience in creating and implementing complex chip-level DFT architecture Proficient in logic design using Verilog Experience in DFT implementation including Scan insertion, ATPG and Simulations Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression Experience in debugging low coverage and DRC fixes Experience of debugging test pattern issues Support the Silicon bringup activities to guarantee highest stability of the test pattern Knowledge of MBIST is a plus. Knowledge of synthesis is a plus Experience with post-silicon debug Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc Any Tessent Scan/ATPG certifications is a plus Excellent presentation and inter-communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Prior experience as DFT engineer

Skills / Experience: Proficient in Scan, specializing in ATPG and Pattern verification at Block and Full chip level. Skilled in Scan insertion, ATPG, DRC analysis, Low Coverage Analysis, JTAG and IJTAG. Experienced in scripting for flow automation, using Siemens tools (Tessent), Synopsys tools (DFTMAX, Tetra MAX, VCS, DFT Compiler), Verdi. Familiar with tools: NC-SIM/Irun, Sim-Vision, XCELIUM. Education Qualification: BTECH/ MTECH in Electrical/ Electronics/ Computer Science Engineering or Equivalent.

Role: Senior DFT Engineer Exp: 5+ years Location: Bangalore Skills: Siemens Tessent (Memory BIST, Scan Insertion) ATPG (TetraMAX/TestKompress) Scan Compression, VTRAN TCL/Python scripting Silicon bring-up & ATE debug

Role Description This is a full-time on-site role for DFT Engineer at Incise Infotech. DFT Engineer will be responsible for developing, implementing, and verifying the Design for testability (DFT) on complex system on chips (SOCs). The role also involves working with the physical design team to ensure the DFT requirements are met and with the verification team to ensure the DFT design is meeting the test coverage metrics. The ideal candidate will have experience in SOC level DFT techniques, ATPG, MBIST, JTAG, and boundary scan. Qualifications Bachelor's or Master's degree in Electrical/Electronics Engineering or equivalent 3+ years of experience in DFT domain Expertise in DFT methodologies - scan insertion, scan compression, boundary scan, and memory BIST Experience in DFT tools like Tessent, ATPG, MBIST, and JTAG Experience in the complete scan chain flow (ATPG, simulation, and test pattern generation) on complex SOCs Knowledge of STA, LEC, and physical design aspects related to DFT Experience in Shell/Perl/Tcl and other scripting languages Good communication skills and the ability to work well in a team environment Interested can share resume on Shubhanshi@incise.in

Experience: 5 + - Should have worked hands-on Full chip DFT implementation, Scan, DRCs, ATPG generation & Simulations along with Pattern Porting/re-targeting and Coverage improvement -Experience with Scan, Compression, ATPG and simulations with Synopsys EDA tools. - Should have participated in successful tape-outs of SoC/ASIC chips at 3nm or below and achieved test targets. - Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA. -Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process -Excellent problem solving and debugging skills. Proactive in nature - Excellent Customer interaction, Communication and Team work skills

5years experience in VLSI EDA/CAD methodology development in areas of DFT, Scan/ATPG/MBIST. Good knowledge of the DFT domain specifically on Scan logic generation, insertion methodology. Exposure to using RTL, Netlist DRC tools like Synopsys Spyglass is preferable, Strong development skills in TCL, Python.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Primary responsibilities will include, Interface with design team to ensure DFT design rules and coverages are met. Generating high quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models through the use of on-chip test compression techniques. MBIST verification (including repair), test pattern generation through Mentor tool. ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations. Work with the Product/Test engineering teams on the delivery of manufacturing test patterns for ATE. Responsible for supporting post silicon debug effort, issue resolution. Responsible for Diagnostic Tool generation for ATPG, MBIST and bring-up on ATE. Developing, enhancing and maintaining scripts as necessary Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Bachelors / Masters degree in electrical or electronics engineering with 3-6 yrs of experience is preferred Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Like Requirements: 3 to 6 years of hands-on experience in DFT methodologies , with expertise in Scan & ATPG . Strong knowledge of DFT tools such as Synopsys, Mentor Graphics, or Cadence. Experience in fault modeling, pattern generation, and coverage analysis . Proficiency in scripting (TCL, Python, Perl, or Shell) for automation. Excellent problem-solving skills and ability to work in a fast-paced environment. Job Responsibilities: Implement and validate DFT architectures for complex SoCs. Perform scan insertion and ensure proper integration into the design. Develop and optimize ATPG patterns to achieve high fault coverage. Work closely with RTL, verification, and physical design teams to resolve DFT-related issues. Support post-silicon bring-up, debug, and ATE (Automated Test Equipment) testing.

Mirafra Technologies Hiring DFT Lead Engineers: Experience - 7 to 12 years Notice Period - 0 to 90 days (45 days or lesser notice period will be preferred 1st) Location - Bangalore Please find the Job Description Below: Minimum 7+ years of relevant work experience in DFT. Good at Scan and ATPG. Hands on experience in various DFT aspects like Scan insertion, MBIST and JTAG, ATPG, Pattern validation at block level as well as Fullchip level. Synopsys tools: DFT MAX, TetraMAX OR Cadence tools: RTL Compiler, Encounter Test OR Mentor Graphics tools: Tessent tool chain, TestKompress - Debussy, VCS/Questa/IUS - PT tool from Synopsys . Tool Experience - Cadence Modus / Synopsys DFTMax/TetraMax / Mentor/Tessent Expertise in coverage improvement techniques Experience in - Stuck at, Transition, Deley faults, Bridging fault, IDDQ ATPG simulation - with SDF - should possess good debug skills Scripting experience - TCL/Shell/Perl/Python Tester/ATE Pattern debug. if Interested, please share your updated resume at sayantikamajumdar@mirafra.com Thanks and Regards, Sayantika Majumdar Senior Talent Acquisition Specialist Mirafra Technologies Email - sayantikamajumdar@mirafra.com Call- +91 - 9007115796

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Roles and Responsibilities o Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. o Work closely with design/verification teams within CPU to develop comprehensive test plan. o Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. o Verify power intent through use of methodologies like UPF. o Work closely with system architects, software teams and Soc team to validate system use cases. o Work closely with emulation team to enable verification on emulators and FPGA platforms. o Debug and triage failures in simulation, emulation and/or Silicon. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. o BE/BTech degree in CS/EE with 3+ years experience. o Experience in power management verification. o Implementation of assembly and C language embedded firmware. o Experience in C/C++, scripting languages, Verilog/system Verilog. o Strong understanding of power management features in CPUs and CPU based Socs. o Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred Requirements: o Good Understanding of CPU architectures and CPU micro-architectures. o In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture o Experience with advanced verification techniques such as formal and assertions is a plus o Knowledge and verification experience in DFT and structural debug concepts and methodologies:JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus Applicants :Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies :Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications: Master's degree in Computer Science, Engineering, Information Systems, or related field. 5+ years of Hardware Engineering or related work experience. About The Role :: Own and deliver scan insertion. Validate equivalence checks and Debug/resolve any DRC issues, Identify solutions and work with front-end team to ensure DFT DRCs are fixed. Analyzing and meeting ATPG coverage goals. Own and deliver MBIST insertion, validate Memory tests. Owns STA constraints and work with STA team to resolve timing violations. Mandatory Skills: Knowledge in MBIST Operations. Expertise in handling Mentor ATPG tools, Synopsys Synthesis & SMS tool sets. Experience in Test coverage analysis and Simulation of ATPG vectors & MBIST tests. Preferred Skills: Exposure to LBIST, Low Power design and Scripting. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field. 5-9 years Hardware Engineering experience or related work experience. like 1 Level of Responsibility: Works independently with minimal supervision. Decision-making may affect work beyond immediate work group. Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively. Applicants :Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies :Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum of 5+ years experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills Applicants :Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies :Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Be a member of the team that plays a significant role in ensuring the quality of Connectivity SoCs through structured DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques. Primary responsibilities will include , Interfac e with design team to ensure DFT design rules and coverages are met. Generating high quality manufacturing ATPG test patterns for stuck-at (SAF) , transition fault (TDF ) models through the use of on-chip test compression techniques. M BIST verification (including repair), test pattern generation through Mentor tool. ATPG (SAF, TDF) and MBI ST verification using unit delay and min/max timing corner s imulations . Work with the P roduct /Test engineering teams on the delivery of manufacturi ng test patterns for ATE . Responsible for supporting post silicon debug effort, issue resolution . Responsible for Diagnostic Tool generation for ATPG , MBIST and bring-up on ATE. Developing, enhancing and maintaining scripts as necessary Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 1-6 year s experience in ASIC/DFT - simulation and Silicon validation Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement In depth knowledge and hands-on experience in ATPG - coverage analysis. In depth knowledge of Memory verification, repair and failure root-cause analysis. Experience with any of these tools is required ATPG - TestKompress MBIST - Mentor ETVerify Simulation - VCS (preferred), modelsim . Expertise in scripting languages such as Perl , shell, etc. is an added advantage Ability to work in an international team, dynamic environment with good communication skills Ability to learn and adapt to new tools , methodologies. Ability to do multi-tasking & work on several high priority designs in parallel Applicants :Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies :Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Hiring: DFT Engineer (Design for testability) for Staff/Sr Staff positions Location: Noida (Hybrid 3 Days Work from Office) Experience: 7 to 15 years We are looking for a technical leader to drive the DFT aspects of high-performance compute SOC/MCU development. The candidate must be experienced, hands-on and have robust understanding of testability features including SSN, MBIST, LBIST, Scan Insertion, ATPG, GLS and post silicon debug on automotive grade SOCs. Key Responsibilities: Hierarchical scan insertion and SSN-based ATPG flow MBIST integration & verification at RTL level LBIST RTL integration, verification, and GLS enablement Implementation & verification of IEEE 1149.1 JTAG, IJTAG Post-silicon debug for DFT patterns Close collaboration with RTL, PD, and Verification teams Proficiency in scripting languages ( TCL, Perl, or Python ) Apply Now! Click on the Apply button or share your resume with Heena at heena.k@randstad.in Tag your connections who might be interested in this exciting opportunity!

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Be a member of the team that plays a significant role in ensuring the quality of Connectivity SoCs through structured DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques. Primary responsibilities will include,– Interface with design team to ensure DFT design rules and coverages are met. – Generating high quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models through the use of on-chip test compression techniques.– MBIST verification (including repair), test pattern generation through Mentor tool.– ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations.– Work with the Product/Test engineering teams on the delivery of manufacturing test patterns for ATE.– Responsible for supporting post silicon debug effort, issue resolution.– Responsible for Diagnostic Tool generation for ATPG, MBIST and bring-up on ATE.– Developing, enhancing and maintaining scripts as necessary Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 2-6 years"™ experience in ASIC/DFT "“simulation and Silicon validation– Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement– In depth knowledge and hands-on experience in ATPG -coverage analysis.– In depth knowledge of Memory verification, repair and failure root-cause analysis.– Experience with any of these tools is required– ATPG - TestKompress– MBIST - Mentor ETVerify– Simulation - VCS (preferred), modelsim.– Expertise in scripting languages such as Perl, shell, etc. is an added advantage– Ability to work in an international team, dynamic environment with good communication skills– Ability to learn and adapt to new tools, methodologies.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 3+ years"™ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Automatic Test Pattern Generation (ATPG) Good to have skills : NA Minimum 7.5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met. Roles & Responsibilities: Expected to be an SME Collaborate and manage the team to perform Responsible for team decisions Engage with multiple teams and contribute on key decisions Provide solutions to problems for their immediate team and across multiple teams Lead the application design and development process Coordinate with stakeholders to gather requirements Ensure project milestones are met Professional & Technical Skills: Must To Have Skills:Proficiency in Automatic Test Pattern Generation (ATPG) Strong understanding of software development lifecycle Experience in application architecture design Knowledge of database management systems Hands-on experience in application testing Additional Information: The candidate should have a minimum of 7.5 years of experience in Automatic Test Pattern Generation (ATPG) This position is based at our Bengaluru office A 15 years full-time education is required Qualifications 15 years full time education

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Automatic Test Pattern Generation (ATPG) Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met. Roles & Responsibilities: Expected to be an SME Collaborate and manage the team to perform Responsible for team decisions Engage with multiple teams and contribute on key decisions Provide solutions to problems for their immediate team and across multiple teams Lead the application development process effectively Coordinate with team members to ensure project milestones are met Professional & Technical Skills: Must To Have Skills:Proficiency in Automatic Test Pattern Generation (ATPG) Strong understanding of software development lifecycle Experience in application design and configuration Knowledge of project management methodologies Hands-on experience in leading application development projects Additional Information: The candidate should have a minimum of 5 years of experience in Automatic Test Pattern Generation (ATPG) This position is based at our Bengaluru office A 15 years full-time education is required Qualifications 15 years full time education

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Automatic Test Pattern Generation (ATPG) Good to have skills : NA Minimum 12 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met. Roles & Responsibilities: Expected to be an SME Collaborate and manage the team to perform Responsible for team decisions Engage with multiple teams and contribute on key decisions Provide solutions to problems that apply across multiple teams Lead the application development process effectively Coordinate with team members to ensure project milestones are met Provide guidance and support to team members Professional & Technical Skills: Must To Have Skills:Proficiency in Automatic Test Pattern Generation (ATPG) Strong understanding of software development lifecycle Experience in leading application development projects Excellent communication and leadership skills Ability to analyze complex technical requirements Additional Information: The candidate should have a minimum of 12 years of experience in Automatic Test Pattern Generation (ATPG) This position is based at our Bengaluru office A 15 years full-time education is required Qualifications 15 years full time education

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Automatic Test Pattern Generation (ATPG) Good to have skills : NA Minimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. You will be responsible for overseeing the application development process and ensuring successful project delivery. Roles & Responsibilities: Expected to perform independently and become an SME. Required active participation/contribution in team discussions. Contribute in providing solutions to work-related problems. Lead the application development team in designing and building applications. Act as the primary point of contact for all application-related queries. Ensure timely delivery of high-quality applications. Provide technical guidance and mentorship to team members. Collaborate with stakeholders to gather requirements and define project scope. Professional & Technical Skills: Must To Have Skills:Proficiency in Automatic Test Pattern Generation (ATPG). Strong understanding of software development lifecycle. Experience in leading application development projects. Knowledge of programming languages and frameworks. Hands-on experience in application configuration and deployment. Additional Information: The candidate should have a minimum of 3 years of experience in Automatic Test Pattern Generation (ATPG). This position is based at our Bengaluru office. A 15 years full-time education is required. Qualifications 15 years full time education