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Lead DFT Engineer - JTAG & Hard IP Testing Plugscale Consulting

8.0 - 12.0 years

35 - 60 Lacs

bengaluru

Work from Office

About the role: Were looking for DFT Engineers across various experience levels (8 to 12 years) to be part of our cutting-edge semiconductor design team. If you're skilled in Scan Insertion, ATPG, MBIST, IJTAG, or Hard IP Test Simulations, we have the perfect opportunity for you! Responsibilities Boundary Scan integration for Hard IPs Experience with JTAG architecture & pre-stitched scan chains Testing PLL, ADC, DAC, PCIe, UCIe, and SerDes macros Proficiency in Spyglass, SDC constraints & scripting

Posted 1 day ago

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