10.0 - 14.0 years

0 Lacs

karnataka

On-site

The Manager, DFT will be responsible for implementing the hardware Memory BIST (MBIST) features that support ATE, in-system test, debug, and diagnostics needs of the memories in design. You will work closely with the design, design-verification, and backend teams to enable the integration and validation of the test logic in all phases of the design and backend implementation flow. The job requires you to have good scripting skills and the ability to design and debug with minimal oversight. You will also be involved in high-quality pattern release to the test team and support silicon bring-up and yield improvement. The ideal candidate for this role should be an ASIC Design DFT engineer with 10+ years of related work experience encompassing a broad mix of technologies. You should have knowledge of the latest state-of-the-art trends in Memory testing and silicon engineering. Hands-on experience in JTAG & IJTAG protocols, MBIST, and scan architectures is essential. Your verification skills should include System Verilog, LEC, and validating test timing of the design. Experience working with gate-level simulations, and debug with VCS and other simulators is required. Understanding the testbench in System Verilog, UVM/VMM is considered an addon. Post-silicon validation and debug experience, along with the ability to work with ATE patterns, is a crucial aspect of this role. Additionally, you should possess strong verbal communication skills and the ability to thrive in a dynamic environment. Proficiency in scripting skills such as Python/Perl is also required for this position.,

Posted 2 weeks ago

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Principal DFT Engineer NXP Semiconductors

5.0 - 10.0 years

0 Lacs

karnataka

On-site

As a Senior DFT engineer with over 10 years of experience in SoC DfT implementation and verification of scan architectures, JTAG, memory BIST, ATPG, and LBIST, you will play a crucial role in ensuring the design quality and functionality of complex semiconductor devices. Your educational background should include a BE/ME/B.Tech/M.Tech degree from reputed institutes with a 1st class degree and a minimum of 5 years of relevant industry experience. Your expertise in Verilog/VHDL RTL coding and proficiency in using Mentor DfT tools and Cadence tools will be essential for success in this role. You will be responsible for tasks such as scan insertion, JTAG, LBIST, ATPG, DRC, and coverage analysis, as well as simulation debug with timing/SDF. It is expected that you have hands-on experience working on at least one SoC project from start to end. In addition to technical skills, you should possess qualities such as proactiveness, collaboration, and attention to detail. The ability to exercise independent judgment, debug issues, and identify root causes of simulation failures is crucial for this position. Strong interpersonal skills, effective communication (both oral and written), and self-motivation are also key attributes that will contribute to your success. At NXP in India, we value individuals who exhibit curiosity, a desire to understand the underlying mechanisms of their work, and a continuous drive for learning and improvement. If you are someone who thrives in a dynamic and challenging environment, where your contributions can make a significant impact, we encourage you to apply and join our team.,

Posted 1 month ago

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