7.0 - 11.0 years

0 Lacs

karnataka

On-site

You should be well versed with timing closure (STA) and timing closure methodologies, along with the ability to develop pre/post-layout constraints for timing closure. You will be required to collaborate with the design team to establish functional/DFT constraints and integrate IP level constraints. Additionally, you should have experience in defining multi-voltage/switching aware corner definitions, selecting RC/C models, and possessing expertise in abstraction techniques such as Hyperscale/ILM/ETM. In this role, you will be responsible for conducting RC balancing and scaling analysis of full chip clocks as well as critical data paths. Proficiency in automation using PERL, TCL, and EDA tool-specific scripting is essential. You should also have experience in DMSA at full chip level and developing custom scripts for timing fixes. As for qualifications, a BE/BTECH/MTECH in EE/ECE with proven experience in ASIC Physical Design is required. Detailed knowledge of EDA tools and flows, specifically Tempus/Primetime, is a must-have. The ideal candidate should have a minimum of 7 years of relevant experience in the field.,

Posted 1 week ago

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