RTL to GDSII Engineer

As an RTL to GDSII Engineer with over 5 years of experience, you will be joining our team in Bangalore. Your primary responsibility will be to develop and maintain Design Compiler (DC) constraint files, perform Pre-Timing Synthesis on RTL designs, execute Pre-Static Timing Analysis (Pre-STA), and support Physical Design (PD) activities. Collaboration with cross-functional teams to achieve design closure and ensure high-quality deliverables will be crucial. To excel in this role, you must have a strong technical expertise in synthesis and timing analysis. Your hands-on experience across the complete RTL to GDSII flow will be essential. Specifically, you should possess a background in synthesis, STA, and physical design processes, as well as expertise in writing DC constraint files. Your proven ability to debug and resolve design and timing issues will be highly valued. If you are someone who is looking for a challenging opportunity in a dynamic work environment and can join within a notice period of 15 days, we encourage you to apply for this position.,