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0.0 years
0 Lacs
hyderabad, telangana, india
On-site
JD Design Verification Understanding the business requirements and functional specifications of the IPs, subsystems and SOC Creating Verification Environment Architecture document Reviewing and Revising: working towards meeting agreed upon acceptance criteria Developing code in System Verilog, UVM (Universal Verification Methodology), C for Unit, Subsystem and SOC level verification Performing RTL simulations using Synopsys and Cadence simulators Debugging and resolving problems found by simulations .Performance test plan development and maintenance Development of transactors, monitors and models for performance verification. Implement performance verification flow including monitoring, sync...
Posted 2 weeks ago
7.0 - 9.0 years
0 Lacs
bengaluru, karnataka, india
On-site
Role - Senior Design Verification Engineer Experience - 7+years Location - Bangalore, Hyderabad, Pune and Kochi Notice Period - Immediate to 60days JD Design Verification Understanding the business requirements and functional specifications of the IPs, subsystems and SOC Creating Verification Environment Architecture document Reviewing and Revising: working towards meeting agreed upon acceptance criteria Developing code in System Verilog, UVM (Universal Verification Methodology), C for Unit, Subsystem and SOC level verification Performing RTL simulations using Synopsys and Cadence simulators Debugging and resolving problems found by simulations .Performance test plan development and maintena...
Posted 3 weeks ago
8.0 - 12.0 years
0 Lacs
hyderabad, telangana
On-site
You are responsible for hands-on SOC C verification, validation, product debug issues, and silicon bring-up experience. Your role involves engaging in multi-processor SOC C verification, validation activities with a strong skill set in C/C++. It is essential for you to have a good understanding of End-to-End debug on various platforms like Bring Up Boards and FPGA prototyping platforms. Moreover, you should be well-versed in NAND, UFS, ARC, ONFI, AXI protocols and debug mechanisms using tools like Metaware debugger. Your responsibilities will also include gaining exposure to Firmware flows during debug activities and being familiar with Verilog/System Verilog RTL. You must be able to analyze...
Posted 1 month ago
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