ASIC RTL Engineer III, Silicon IP/Subsystem Google

4.0 - 6.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. 3 years of experience in ASIC design flows and methodologies, IP integration (e.g., subsystems, memories, IO's and Analog IP) and RTL design. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science. Experience worki...

Posted 4 days ago

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Senior Front End Integration - STA Engineer Advanced Micro Devices, Inc

5.0 - 10.0 years

0 Lacs

hyderabad, telangana

On-site

As a Senior Silicon Design Engineer at AMD, you will play a key role in contributing to the development and verification of cutting-edge technologies that drive innovation in the computing industry. Your passion for modern processor architecture, digital design, and verification will be instrumental in ensuring the highest quality products are delivered to the market. In this role, you will collaborate with a diverse team of engineers to implement front-end designs from RTL to netlist, conduct formal verification checks, and debug any timing, area, or congestion issues that may arise. Your ability to analyze inter-block timing and develop timing constraints will be crucial in optimizing the ...

Posted 3 months ago

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Senior Front End Integration - STA Engineer Advanced Micro Devices (AMD)

5.0 - 10.0 years

5 - 10 Lacs

Hyderabad, Telangana, India

On-site

KEY RESPONSIBILITIES: Front-end implementation from RTL to netlist, including RTL Lint, CDC/RDC analysis, timing constraints, Power Analysis, STA for Multi-Media IPs Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them. Analyze the inter-block timing and come up with IO budgets for the various partition blocks. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks ...

Posted 3 months ago

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Synthesis Engineer, Senior Lead Qualcomm

1.0 - 6.0 years

0 Lacs

karnataka

On-site

Qualcomm India Private Limited is seeking a Hardware Engineer to be a part of the Engineering Group, specifically in the Hardware Engineering team. As a Qualcomm Hardware Engineer, you will be involved in various aspects of planning, designing, optimizing, verifying, and testing electronic systems. This role will require you to work on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to contribute to the development of cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. To be considered for this position, you must have...

Posted 3 months ago

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