1175 Rtl Jobs - Page 41

Conceptualizes, documents, and designs tools, flows, and methods (TFM) for use in the physical design implementation of IPs, SoCs, and the interaction/handoff/reuse between IPs and SoCs. Establishes regression flows, drives improvement in RTL to GDS flows, and creates and implements methodologies for improving robustness, power, performance, area, and timing for optimizing physical design constraints. Develops new physical design techniques through innovative scripts, checkers, flows, and other CAD based automation to simplify and expedite the design process. Analyzes retrospective data on current generation quality and efficiency gaps to identify proper incremental, evolutionary, or transfo...

. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. . 3-10 years of experience in RTL design and Design Verification implementation for VLSI systems.

Key Responsibilities: Translate design specifications into comprehensive power specifications and architect UPF files accordingly. Build and refine power intent using Unified Power Format (UPF) at RTL and gate-level, ensuring consistency across synthesis and physical design flows. Perform power-aware checks using CLP and debug issues arising during MV cell insertion such as isolation, retention, and level shifters. Collaborate with Power Aware DV teams to address feedback and enhance the robustness of power intent. Estimate dynamic and leakage power early in the design cycle and generate power reports using tools like PTPX . Monitor and analyze power trends through implementation milestones;...

Desired Skills and Experience: Proficiency with STA, SDC. Proficiency with RTL, System Verilog. Strong understanding of front-end EDA design methodologies. Strong Perl, Tcl or Python scripting skills. Prior experience with logic synthesis tools is required. Prior experience using or supporting SDC tools would be a significant plus. Prior experience with RTL simulation, SVA would be a plus. Prior experience supporting front-end EDA tools would be a plus. Sound communication skills, verbal and written. Ability to produce product requirement documents. BS EE/CE. 4 years experience with STA/Synthesis.

What You ll Need: Proficiency with STA, SDC. Proficiency with RTL, System Verilog. Strong understanding of front-end EDA design methodologies. Strong Perl, Tcl, or Python scripting skills. Prior experience with logic synthesis tools. Prior experience using or supporting SDC tools (a significant plus). Prior experience with RTL simulation and SVA (a plus). Sound communication skills, both verbal and written. Ability to produce detailed product requirement documents. BS in Electrical or Computer Engineering with 10+ years of experience in STA/Synthesis/Front-End Flows.

Developing and testing software for validation and automation purposes. Performing device-level and system-level validation and debug in post-silicon environments. Executing software tests in verification environments to ensure product quality. Working with FPGA-based setups to run validation tests and update FPGA RTL modules as needed. Creating detailed test and validation reports with statistical analysis. Interfacing with customers to capture requirements and provide post-release support. The Impact You Will Have: Contributing to the development of cutting-edge technology that drives innovation in various industries. Ensuring the reliability and performance of high-speed serial interface ...

Generate test benches and test cases. Perform RTL and gate-level SDF-annotated simulations and debug. May perform mixed-signal (digital + analog) simulations and debug. Interact with our application engineers and provide guidance to customers. Participate in the generation of data books, application notes, and white papers. Perform physical verification and design rule checks to ensure design integrity and manufacturability. Understand tools like VC Spyglass, Verdi, & views like SDF, Liberty, etc., and other frontend views. Write RTL Code, with solid Verilog, PERL, and Python skills, and TCL is a good addition. Understand static timing analysis and synthesis, DFT/ATPG skills would be a plus....

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Debug fails using waveform, trace tools and debug RTL code Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 + years of experience in Functional Verification of Processors or ASICs. Minimum 3+ years of experience in any of the following Comp...

* Perform Sub system level floor planning, placement, and routing for high-performance microprocessor design. * Collaborate with cross-functional teams to achieve design goals. * Close the design to meet timing, power, and area requirements. * Implement engineering change orders (ECOs) to rectify functional bugs and timing issues. * Ensure the quality and efficiency of the RTL to GDS2 implementation process. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8+ years of industry experience Good knowledge and hands on experience in physical design , timing and methodology which include logic synthesis, placement, clock tree s...

Fundamental Knowledge of VHDL: Understanding of VHDL programming basics and digital design principles. Familiarity with Design Tools: Basic exposure to tools such as AMD Vivado and SDK, with some knowledge of Petalinux, Verilog, and Intel Quartus. Introductory Experience in Interface Design: Understanding of high-speed interface concepts, cross-clock domain interactions, and the creation of simple test benches. Synthesis and Debugging Awareness: Basic understanding of synthesis processes and an introduction to debugging tools like ILA and Signal Tap for high-speed designs. Knowledge of Embedded Systems: Familiarity with embedded processor architectures and programmable logic. Hands-On Experi...

Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We craft the networking hardware for Enterprises and Service Providers, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-br...

This position is in a cutting-edge synthesis product, in the area of Logic synthesis and Optimization. The candidate will be required to work on enhancing the optimization flow for performance, power, area (PPA) or runtime. This will involve identifying the opportunity for improving PPA, proposing a good solution/algorithm, implementing it, thoroughly testing it, and supporting it post-deployment. Job Requirements 1. 3+ years of work experience in EDA, preferably in logic optimization and logic synthesis. 2. Strong software skills: minimum 5 years of coding experience in C++. 3. Proficiency in data structures and algorithms. 4. Strong analytical and problem-solving skills. 5. Good understand...

Role & responsibilities Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies 5-7 years of exp...

12+ years of experience in ASIC design Proficient in Verilog coding, RTL design and complex control path and data path designs Knowledge of any of the interface Protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display, Ethernet, SATA Knowledge of RTL checks ex- LINT, SDC, CDC Familiar with synthesis flow, LEC and timing constraints Experience in writing Verilog testbench and running simulations.

We are looking for a candidate with excellent communication skills and ability to ramp up on new technologies quickly and independently. This an excellent opportunity to work in a supportive and friendly work environment, where we are vested in each other s success, and are passionate about technology and innovation. Qualifications: BE/BTech/ME/MS/MTech Job Responsibilities: Experience: 15+yrs Candidate must be able to generate RTL/handle scalable designs up to 48 billion Gates. Should be able to modify/update the designs to stress Flip-Flops/Wires/Gates/Input Outputs. Should be able use various available scalable compile/Runtime flows for large scalable designs. Should be able to profile an...

We are seeking a highly skilled and motivated STA Synthesis Engineer to join our offshore development teams . The ideal candidate will have expertise in static timing analysis (STA) to ensure the timing integrity of digital integrated circuits. Develop and execute timing constraints, ensuring compliance with design specifications and performance goals. Prepare detailed STA reports, including analysis and recommendations for improvements. Provide training and support to junior STA engineers and team members Role & Responsibilities : - Timing Constraint Generation : Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements fo...

Job Description- Mandatory Skills 4+ Years of experience with React.js, including hooks, component design, and state management (Redux / Recoil) Strong knowledge of JavaScript (ES6+) Solid understanding of GraphQL and its ecosystem (e.g., Apollo Client, GraphQL Queries & Mutations). Hands on experience of unit testing and testing frameworks (Preferably Jest & RTL) Excellent communication skills Preferred Skills Knowledge of design patterns Working knowledge in Mapstruct, Spring Cloud Streams, Spring Contract Testing Experience in mobility frameworks like React-Native Experience in Java, Springboot,, JAXRS, Mybatis, PostgreAQL, Junit. Experience in build tools like Apache Maven, Webpack

Roles and Responsibilities Work in a team or individually to design, develop and test web based application Design, develop, test and document quality software to user and functional requirements within specified timeframes and in accordance with the best coding standards Generate rapid prototypes for feasibility testing Generate all documentation relevant to software operation Adhere to prescribed development systems, processes procedures and ensure efficient, effective, high-quality delivery Communicate effectively with all stakeholders Perform tasks as specified by the Delivery Lead/Team Lead Qualifications and/or Experience 4-5yrs of experience as a UI Developer with a strong focus on UI...

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL/Test Pervassive Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high p...

Deliver comprehensive training on VLSI Design and Verification, covering topics like Digital Design, Verilog/System Verilog, RTL Design, and UVM. Prepare, update, and structure course materials and assignments as per industry standards.

Semicon Technical Program Manager | Bangalore or Hyderabad | Experience: 7 to10 Years Are you a hands-on technical expert who thrives at the intersection of Digital Design and Program Leadership ? We're looking for a Semicon Technical Program Manager to drive end-to-end execution across high-impact SoC design programs. This is a billed, customer-facing role that goes beyond task trackingyoull own milestones, lead cross-functional sync-ups, and bring structure to complex digital engineering workflows. What You’ll Do: Drive technical coordination across RTL, DV, PD, and STA teams. Track and manage project milestones, deliverables , and dependencies. Lead technical meetings , ensuring alignment...

Summary Established in 2001, EnSilica is a publicly listed company (LON:ENSI), designing industry leading, application specific integrated circuit chips (ASIC), for customers ranging from start-ups to blue chip companies, in industries including: automotive, medical, space and mobile technology companies. With its head office on Milton Park, Oxfordshire, and other offices in Bristol, Sheffield, Brazil (Porto Alegre) and India (Bangalore), EnSilica currently employs more than 160 people. We are looking for a very experienced verification engineer who can not only strengthen the team through their technical expertise but also bring leadership and grow the verification business within EnSilica....

Alphawave Semi is looking for Senior Engineer I - ASIC Design to join our dynamic team and embark on a rewarding career journey. Analyze and assess problems. Apply quality principles and methodology in processes to enhance output. Assess new product designs to meet project and product requirements. Create engineering designs. Identify the design needs of clients. Manage disputes and conflicts. Manage product design and development to meet project and product requirements. Oversee Workplace Safety and Health Systems (WSH) for the company.

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: Senior/lead DFT Engineer (SCAN) Location: Bangalore Work Type: Onsite Job Type: Full time Job Description: Minimum 8+ years of experience in Scan insertion and with good understanding of RTL • Should be able to understand DFT Architecture and perform Scan insertion • Good understanding of RTL • Good understanding of Pin Muxing • Debug S1/S2 violation during Scan insertion • Test point insertion • Support ATPG engineer to debug Scan ATPG DRC's and cove TekWissen Group is an equal opportunity employer supporting workforce diversity.

RoleFront-End RTL Design Automation Engineer Experience10+years LocationBangalore Notice PeriodMax 15days preferred Role Overview We are looking for a Senior CAD Engineer to deploy and support our front-end tools, to develop scripts to automate regression and debug flows, and to work along with our design, implementation and verification teams. What You'll Do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load dis...