1161 Rtl Jobs - Page 22

Eximietas is currently seeking a Senior Physical Design Architect with over 10 years of experience for a position in Hyderabad. The ideal candidate should hold a Bachelor's or Master's Degree in Engineering in Electronics, Electrical, Telecom, or VLSI Engineering. As a Senior Physical Design Architect, you will be working on designs ranging from 10nm to 5nm nodes with various customers. Your responsibilities will include solving critical design problems to meet performance, area, and power targets, developing placement, clock-tree synthesis, and routing methodologies, as well as providing training and technical support to customers. The successful candidate should have a strong background in...

You Are: An experienced Emulation Engineer with Zebu experience. The Work: Port ASIC and IP RTL code to emulation platforms (Zebu). Build model from released RTL. Generate loadable image(s) for target emulation platform. Run sanity tests to qualify release of the image(s). Release the emulation models to various teams doing functional validation, firmware development and design verification. Assist debug of failures with stakeholder by providing instrumented models and captured waveforms extracted from emulation model. Coordinate with EDA and third-party tools team to validate implementation flows. Heres what you need: A minimum 2 years of experience in Emulation (Zebu) using System Verilog/...

Understand the design specification , TB architecture Learn in IBM Fusion and Trek verification languages and tools, apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8+ years of work experience in IP, Sub-system & SOC level - Exp in creating multiple UVM/SV based env from scratch, Strong in Block Level verification Exp in developing checkers, Scoreboards, Monitors, Test plan development, Code c...

As Logic Lead, you will be responsible for design and development of Compression, Security, and sustainability features for high performance Processors chips. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature Guide and mentor junior engineers. Represent as Design Lead in various forums. Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in silicon bring-up and validation of the hardware Estimate the overall effort to dev...

We are seeking an experienced RTL Design Engineer to join our Digital Design team and contribute to the development of Aevas 4-D Lidar processing chip. The role involves implementing and integrating sub-components of the signal processing pipeline in ASICs and FPGAs, including filters, FFTs, and control logic. The engineer will be responsible for writing micro-architecture specifications, coding in SystemVerilog RTL, and validating Aeva-specific sub-components while ensuring functional safety, performance, and robustness. Collaboration with architects, design engineers, verification teams, and system software engineers is essential to meet SOC-level performance, power, and functionality goal...

Greetings From Dexcel Designs! We are inviting applications for FPGA Design and Verification Engineer Job Overview: We are seeking FPGA Design and Verification Engineers with 3-6 years of experience in RTL design, FPGA verification, and high-speed interface development . This role involves designing, implementing, and validating FPGA-based systems while working closely with cross-functional teams in hardware and embedded software development. Key Responsibilities: Develop and implement RTL designs for FPGA-based systems. Perform functional verification and validation of FPGA designs. Work on timing analysis, synthesis, and debugging of FPGA architectures. Collaborate with hardware, embedded ...

In this role you will work on SoC/Sub-system level Emulation model development and design bring up on Zebu/Veloce HW platforms. Additionally, you will work closely with design, verification, validation, and SW teams to implement emulation testbench (XTORs, Speed Adaptors) and features required to develop content on emulation models. You would develop tests to qualify models. Key Skills 8-15 years of experience on SoC/Sub-system Emulation of multi-million gate and complex design with multiple clocks and power domains Experience in microcontroller architecture, Cores ARM A/M series, Interconnect (NIC, FlexNoC), Protocols like AHB, AXI, Memory (Flash, SRAM, DDR4/5), and memory controllers Exper...

We are seeking highly motivated, energetic, and team-oriented individual contributors who can work on synthesis, LEC, and constraints for NXPs digital IPs, working in close collaboration with the RTL team. Key Responsibilities Work closely with the architects and RTL team on synthesis, LEC, and constraints of NXP digital IPs Carry out floor planning, and physically aware synthesis on high-performance IPs Perform timing and power analysis on the design database (db), improve the recipe, and provide timing feedback to the RTL team Leads or solo owners are expected to work with minimal micro-management needs. They should be able to communicate with other project members to manage task divisions...

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills. Mandatory Key Skills VHDL,RTL coding,Mentor DfT tools,Caden...

Were hiring a " Semiconductor Sales - Key Account or Business Development Manager" to lead and grow semiconductor business engagements across INDIA . This role is ideal for professionals with a strong track record in ASIC/SoC/IC services or product sales . Key Highlights: Experience : 5+ years in semiconductor industry sales Industry Focus : Experience working with semiconductor services or product companies (ASIC/SoC/IC) Sales Style : Hybrid role combining hunting (new client acquisition) and farming (account growth) Service Offering : We provide Semiconductor Design and end-to-end ASIC turnkey solutions from Specifications to Silicon , including spec definition, RTL, physical design, verif...

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills. Mandatory Key Skills JTAG,ATPG DRC,LBIST,RTL coding,VHDL,DF...

Job Description: SOC Verification engineers with 3+ years of experience Knowledge of ARM architecture, CPU fundamentals & Cache coherency Experience with C/C++, assembly, and scripting languages. Familiarity with low-power design and verification Develop CDV UVM verification environments at system level Verify CPU connectivity to IP blocks Develop SoC test plans and test cases and track metrics including code and functional covera Job Requirement: Bachelors or Masters in EE/CS or related field 3+ years of SoC in ASIC/FPGA verification experience Proficiency in SV and UVM Experience with simulation, emulation, and formal verification Strong debugging and problem-solving skills Experience (yea...

Your Impact Write micro-architecture specifications and participate in reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integration and timing methodology/analysis. Develop and analyze functional coverage. Help define, evolve, and support our design methodology. Collaborate with the verification team to address design bugs and close code coverage. Work closely with the physical design team to close design timing and place-and-route issues. Triage, debug, and root cause simulation, software bring-up, and customer failures Perform diagnostic and post-silicon validation tests in the lab Minimum Qualifications: Bachelor's Degree / Master...

What You ll Need: MSEE or BSEE with 20+ years of digital design experience. 15+ years of digital and/or physical design experience, including hands-on contributions. Strong understanding of digital design and architecture, physical implementation flows, and timing signoff. Experience with low-power design techniques at RTL and design implementation flow. Proficiency with EDA tool flows and advanced node challenges at 5nm and below. Expertise in developing timing constraints and UPF for power, timing, and area optimization. Excellent software and scripting skills (Perl, Tcl, Python).

Synopsys is market leader for these IP developments which are integral part of Silicon lifecycle monitoring, You Are: As a new, exciting and challenging position, we are looking for a talented person that can show a great level of initiative and ability to work in a busy and fast changing environment This rewarding role being fundamental to the successful and smooth operation of the engineering teams, You will play a vital role in helping to strengthen and develop forecasting capabilities, based upon improved monitoring capacity and forward-looking project schedules, Develop and maintain automation scripts for CAD tools using languages like Python, Perl, or TCL, Collaborate with designers an...

What You'll Do Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. Responsibilities Looking for a Front-end Design ASIC Engineer. Architectural work: in-depth understanding of the architecture, and identification of problems and solutions. All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for l...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job AreaHardware Engineering (Verification) QCT's Bangalore Wireless R&D Bluetooth HW team is looking for experienced Wireless HW design verification engineers to work on Qualcomms best in class chipsets for mobile phones, wearables and IOT. Candidate will be working with ASIC designs on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies including simulation, emulation, GLS and Formal techniq...

You will be implementing the industry's leading edge graphics processor, specific areas include 2D and 3D graphics, streaming processor, high speed IO interface and bus protocols. In this position, the designer will be responsible for architecture and micro-architecture design of the ASIC, RTL design and synthesis, logic and timing verification. The successful candidate for this position will specify and design digital blocks in our Multimedia Graphics team that will be integrated into a broad range of devices. All Qualcomm employees are expected to actively support diversity on their teams, and in the Company. Minimum Qualifications Bachelor's degree in Science, Engineering, or related fiel...

General Summary: Join Qualcomm's HEXAGON DSP team, responsible for high-performance DSP cores integral to Qualcomm's multi-tier SoC roadmap in mobile devices. This role focuses on design verification of complex proprietary DSP IP with an emphasis on power-aware verification. Key Responsibilities: Lead design verification for DSP subsystem IP in collaboration with global architecture, design, and power teams. Architect, implement, and enhance SystemVerilog testbench environments following UVM/OVM methodologies. Develop comprehensive verification plans and execute simulation, assertions, formal verification, and HW-SW co-verification. Drive power-aware RTL simulation using UPF methodologies. P...

Roles And Responsibilities Performance exploration. Explore high performance strategies working with the CPU modeling team. Microarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification. RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals. Functional verification support. Help the design verification team execute on the functional verification strategy. Performance verification support. Help verify that the RTL design meets the performance goals. Design delivery. Work with multi-functional engineering team to imp...

Fundamental Knowledge of VHDL: Understanding of VHDL programming basics and digital design principles. Familiarity with Design Tools: Basic exposure to tools such as AMD Vivado and SDK, with some knowledge of Petalinux, Verilog, and Intel Quartus. Introductory Experience in Interface Design: Understanding of high-speed interface concepts, cross-clock domain interactions, and the creation of simple test benches. Synthesis and Debugging Awareness: Basic understanding of synthesis processes and an introduction to debugging tools like ILA and Signal Tap for high-speed designs. Knowledge of Embedded Systems: Familiarity with embedded processor architectures and programmable logic. Hands-On Experi...

What You'll Do Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. Responsibilities Looking for a Front-end Design ASIC Engineer. Architectural work: in-depth understanding of the architecture, and identification of problems and solutions. All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for l...

Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Emulation Good to have skills : NAMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will analyze, design, code, and test multiple components of application code across one or more clients. You will perform maintenance, enhancements, and/or development work in a dynamic environment, contributing to the success of the projects. Roles & Responsibilitie...

We are looking for a skilled RTL Design Engineer with 3 to 7 years of experience to join our team at Capgemini Technology Services India Limited. The ideal candidate will have a strong background in IT Services & Consulting and be proficient in RTL design. Roles and Responsibility Design and develop high-quality RTL code for various projects. Collaborate with cross-functional teams to identify and prioritize project requirements. Develop and maintain technical documentation for RTL designs. Troubleshoot and debug issues related to RTL code. Participate in code reviews and ensure adherence to coding standards. Stay updated with industry trends and emerging technologies in RTL design. Job Requ...

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in g...