806 Rtl Jobs - Page 20

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications: Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 5+ years of Hardware Engineering or related work experience. 2+ years of experience with circuit design (e.g., digital, analog, RF). 2+ years of experience utilizing schematic capture and circuit simulation software. 2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc. 1+ year in a technical leadership role with or without direct reports. Principal Duties and Responsibilities: Leverages Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Integrates features and functionality into hardware designs in line with proposals or roadmaps. Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area. Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality. Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules. Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity. Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues. Writes detailed technical documentation for Hardware projects. Level of Responsibility: Works independently with minimal supervision. Provides supervision/guidance to other team members. Decision-making may affect work beyond immediate work group. Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. J Principal Responsibilities: Senior leader with 20+ CAD/Methodology development experience for team in Bengaluru. Drive tools, flows, methodologies globally as part of world-wide CAD organization. Develop and implement advanced CAD flows and methodologies for front end RTL Design to Verification Methodologies and framework development. Utilize scripting languages (python) to automate CAD/IT processes and increase efficiency. Collaborate with cross-functional teams to ensure successful integration of CAD flows. Stay up-to-date with cutting-edge technology (AI/ML), conduct thorough analysis of CAD tools and make improvements. Work closely with users to troubleshoot and resolve any issues that arise in tools, flows, environment, and infrastructure. Preferred Qualifications: Experience building full stack AI applications, with a focus on practical, production-grade solutions Strong proficiency in Rust for performance-critical systems and Python for AI development and scripting . Solid understanding of large language models (LLMs), their mechanics, and their real-world applications. Experience implementing tool use capabilities for LLMs and agent frameworks Knowledge of evaluation methodologies for fine-tuned language models Good grasp of Retrieval-Augmented Generation (RAG) and latest AI Agent frameworks Ability to stay current with the fast-evolving AI landscape]. Including advancements in LLMs and neural networks Strong understanding of CAD/EDA tools and methodologies. Hands on experience with regression systems, CI/CD, Revision Control System (git, perforce) workflow. Strong fundamentals in digital design, design verification methodologies and EDA tools. Knowledge of SOC architecture is a plus Preferred – Masters in VLSI or Computer Science Minimum – Bachelors in Electronics/Electrical Engineering/Computer Science Atleast 15 years’ experience in development of tools/flows/methodologies in either RTL, DV, synthesis, PnR or Signoff. Should have a proven record of driving new innovative tool/flow/methodology solutions. Should have managed a medium sized team. Level of Responsibility: Works independently with minimal supervision. Work with chip leads in support of design verification. Collaborate with chip leads to understand the design methodology. high-level requirements, determine other areas to support current or future designs that can benefit from automation and tooling. Provides supervision/guidance to other team members. Decision-making is significant in nature and affects work beyond immediate work group. Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.This requirement is for DDR PD team for Bangalore. Number of openings: Sr. Lead (6 to 8 years) 2 Staff (8 to 10 years) 1 Sr Staff (10 to 12 years) 1 Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling Hands-on experience with STA tools - Prime-time, Tempus Have experience in driving timing convergence at Chip-level and Hard-Macro level In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling, Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus) Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation. Proficient is scripting languages – TCL, Perl, Awk Basic knowledge of device phy STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs Qualcomm Hexagon DSP IP's . Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Work on automation scripts within STA/PD tools for methodology development. Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment Experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS ICC, Innovous , PT/Tempus Familiar with process technology enablementCircuit simulations using Hspice/FineSim, Monte Carlo.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm's Bangalore WLAN PHY (Baseband) team is seeking VLSI Digital Design Engineers to lead IP development for the latest WiFi standards. Our WLAN PHY team, comprised of highly passionate and seasoned domain experts, prides itself on years of experience in taking WLAN PHY designs from concept to silicon independently. WLAN PHY team is responsible for delivering the end-to-end Tx/Rx DSP chains – all the way from antenna samples post ADC to raw bits for upper layers and on the reverse path from raw bits to DAC. The team specializes in working with challenges of practical high-speed wireless communication systems and finding innovative solutions to counter them. The team works extensively on typical signal processing functions like filters, matrix transformations (e.g.QR, Cholesky decomposition), channel estimation, equalization (MMSE, MRC, ML), decoders/encoders (e.g.LDPC, Viterbi) , demodulators, FFT etc. on a day-to-day basis, and contributes to the development/ enhancement/ evaluation of signal processing algorithms to cater to new requirements. We are looking for someone as passionate as us and takes pride in their work. WiFi's ubiquity in modern times is undeniable, and the IEEE 802.11 Working Group is continually developing new standards to satisfy the growing demand for high throughput and low-latency real-time applications, such as VR and AR. Qualcomm is at the forefront of the WiFi revolution, aiming to become the global leader in WiFi chip solutions. The WLAN PHY team in Bangalore is instrumental in realizing this vision. : Looking for a candidate with 1 to 3 years of hands-on experience in micro-architecting and developing complex IPs. Expertise in digital design, VLSI concepts, and experience in creating power/area-efficient IPs across multiple clock domains are essential. Proficiency in RTL coding and familiarity with RTL QA flows such as PLDRC, CDC, and CLP (optional) is expected. Candidates should be capable of proposing design alternatives to meet area/power/performance specifications and presenting these options for review. Experience in leading, guiding, or managing junior team members is advantageous. Repeated success in taking IP designs from requirements to silicon is required. While not mandatory, having developed IPs for wireless technologies (WLAN, LTE, NR, BT, UWB, etc.) or past HLS experience would be beneficial. Skills: Must have: Proficient in Verilog RTL coding, uArch, CDC check, PLDRC, Timing constraints, Python/Perl. Experience in design/debugging complex data-path/control-path IPs. Good communication, analytical & leadership skills. Good to have: System Verilog, Visio, Knowledge of signal processing concepts/algorithms and Wi-Fi standards (802.11a/b/g/n/ac/ax), experience with HLS. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Responsibilities: STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Work on automation scripts within STA/PD tools for methodology development. Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment Experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS ICC, Innovous , PT/Tempus Familiar with process technology enablementCircuit simulations using Hspice/FineSim, Monte Carlo. Education B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI. Preferred Qualification/Skills 5 - 10 years of experience in STA/Timing Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling Hands-on experience with STA tools - Prime-time, Tempus Have experience in driving timing convergence at Chip-level and Hard-Macro level In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling, Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus) Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation. Proficient is scripting languages – TCL, Perl, Awk Basic knowledge of device physics

Handson experience of baremetal FW development in Pre Si w/ UVM TB, debugging FW using Verdi/Sim Vision along with RTL,basic signal tracing in Verilog, High-Speed Serial I/F for 2yrs : UCIe, PCIe, CXL, HBM, Qlink (Qualcomm), DigRF (MIPI)

We Are Hiring: Principal Engineers Chip Design (Back End / Front End / Analog IP/IC) Preferred Skills and Experience: Minimum 1+ years of experience in Project Management (Waterfall and Agile Hybrid methodology) Exposure to continuous improvement and cross-functional collaboration Educational Qualifications: Master's degree in VLSI Design from reputed institutes (IITs/NITs preferred) Bachelor's in Electronics and Communication or a related field 1. Job Title: Principal Engineer – Chip Design Back End Required Skills & Experience: Minimum 8+ years of strong experience in backend flows for MCU or low-power SoC designs Leadership experience with DFT, Physical Design, and Formal Verification teams Exposure to Frontend and Analog design processes Ability to collaborate effectively across functional teams Experience in product support during both pre- and post-production stages (including RMA support) 2. Job Title: Principal Engineer – Chip Design Front End Required Skills & Experience: Minimum 8+ years of experience in system architecture for ARM-based MCU product development Expertise in RTL design, RTL coding, and RTL integration Strong debugging and design capabilities Experience leading verification teams, including static and dynamic verification, test management (UPF, GLN, Test Modes) Familiarity with industry-standard EDA tools (e.g., Synopsys for LINT, CDC, SDC validation, and power analysis) Exposure to Backend and Analog design processes Cross-functional collaboration with PD, DFT, and STA teams for timing and power closure Experience in pre- and post-production product support and RMA handling 3. Job Title: Principal Engineer – Analog IP/IC Design Required Skills & Experience: Minimum 8+ years of experience in custom analog/mixed-signal IC design Proficiency in variation-aware design, verification planning, and analog layout parasitic extraction (LPE) Hands-on experience with analog/mixed-signal EDA tools (e.g., Cadence, Synopsys) Strong debugging and design validation skills Product support experience across development lifecycle, including RMA stage

Role & responsibilities FPGA, RTL, DO-254,VHDL, VERILOG, XILINX, LIBERO, AVIONICSJ Preferred candidate profile

Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools Identify and prioritize needs of internal users and develop capabilities for them Proficiently use scripts to integrate tools, repos and compute infrastructure Configure and maintain project progress Dashboards. Interface with EDA vendors for license and tool installations Deploy tools and methodologies across geographies for global teams working together Location- Remote, Delhi NCR, Bangalore, Chennai, Pune, Kolkata, Ahmedabad, Mumbai, Hyderabad Education- B.Tech/B.E in Computer Engineering (or allied discipline e.g. Electrical, Electronics) 10+ years of relevant experience in CAD or allied disciplines 4+ years in a CAD role for a several 100 million gate Silicon ASIC project Knowledge and understanding of ASIC flow Proficiency in python, bash, c, Makefiles

Job Description. Arm’s CE-Systems DFT team implements DFT for test chips and hard macros to prove out Arm soft IP power, performance, area, and functionality within the context of an SoC using the latest DFT and process technologies. The DFT team works closely with RTL, Verification, Physical Implementation, and Test engineering teams throughout the life cycle of a project, from an early investigation stage all the way through tape-out and silicon test/characterization on ATE.. Responsibilities. Architect, implement, and validate innovative DFT techniques on test chips as well as hard macros. Insert DFT logic into SoC style designs at the RTL level and at the Synthesis gate level, validate all features, and generate ATE targeted test patterns to be run on silicon. Work closely with front-end design and verification teams on DFT RTL level insertion, back-end synthesis, place-and-route, and static-timing-analysis teams on gate level insertion and timing closure, and Test and Debug teams on silicon characterization and validation.. Required Skills And Experience. This role is for a Senior Principal DFT Engineer with 15+ years of experience in Design for Test. Experience coding Verilog RTL, TCL and/or Perl. Proficient in Unix/Linux environments. Core DFT skills considered for this position should include some of the following Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics. Bachelors or Master’s degree or equivalent experience in Electronic Engineering, Computer Engineering, or a related field. “Nice To Have” Skills and Experience. Familiarity with IEEE 1149, 1500, 1687, 1838. Synthesis & Static Timing Analysis. Familiarity with SoC style architectures including multi-clock domain and low power design practices.. Validated understanding of Siemens DFT tools. Familiarity with Arm IP like the following Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, CoreSight debug. Experience with 2.5D and 3D test. Ability to work both collaboratively on a team and independently. Hard-working and excellent time management skills with an ability to multi-task. An upbeat demeanor to working on exciting projects on the cutting edge of technology. Experience with Siemens, Cadence, and/or Synopsys DFT and simulation tools. In Return. We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding!. Partner and customer focus. Teamwork and communication. Creativity and innovation. Team and personal development. Impact and influence. Deliver on your promises. Accommodations at Arm. At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.. Hybrid Working at Arm. Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.. Equal Opportunities at Arm. Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.. Show more Show less

Minimum qualifications:. Bachelor’s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.. 15 years of experience in ASIC RTL design.. Experience with RTL design using Verilog/System Verilog and microarchitecture.. Experience with ARM-based SoCs, interconnects and ASIC methodology.. Preferred qualifications:. Master’s degree in Electrical Engineering or Computer Engineering.. Experience driving multi-generational roadmap for IP development.. Experience leading interconnect IP design team for low power SoCs.. About The Job. Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.. Responsibilities. Lead a team of people to deliver fabric interconnect design.. Develop and refine RTL design to aim power, performance, area, and timing goals.. Define details such as interface protocol, block diagram, data flow, pipelines, etc.. Oversee RTL development, debug functional/performance simulations.. Communicate and work with multi-disciplined and multi-site teams.. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .. Show more Show less

Location: Mohali, Punjab Work Shift: Night Shift (MST/PST) Experience Required: 2+ Years Education: Bachelor's in IT/Engineering or related field Job Description: We are hiring 3 experienced Recruiters/Sr. Recruiters to join our dynamic team supporting the Meta account . This is a hands-on recruitment role focused on sourcing and hiring top-tier talent for cutting-edge technology positions. Key Responsibilities: End-to-end recruitment for roles in: Computer Vision, Firmware, Embedded Systems SoC, CPU/GPU, ASIC, FPGAs, RTL AR/VR, AI/ML, Deep Learning, Hardware Design Engage with candidates through various sourcing channels Screen, interview, and coordinate with hiring managers Maintain strong pipelines and ensure timely closures Key Requirements: Minimum 2 years of IT recruitment experience Strong understanding of deep tech and hardware domains Excellent communication and interpersonal skills Prior experience with Meta or similar high-tech clients preferred Perks & Benefits: Benefits & Perks: 1. Incentives* 2. Monetary Awards* 3. 5-Year Retention Bonus 4. Referral Policy* 5. Internet Reimbursement* 6. Router UPS Reimbursement* 7. Term Life Insurance 8. Accidental Insurance 9. Group Medical Insurance (Family Floater) 10. On-call doctor support 11. Sodexo Benefit 13. Leave Policy 14. NPS - National Pension Scheme 15. LTA Leave Travel allowance. 16. Leave Encashment 17. Bank Assistance 18. Employee's State Insurance* 19. Gratuity 20. Provident Fund 21. Cab facility *Admissibility of the benefit may vary commensurate the department, designation, and role. How to Apply: Send your updated resume to Bharti.sharma@spectraforce.com with the subject line: Recruiter Meta Account Application

Location: Mohali, Punjab Work Shift: Night Shift (MST/PST) Experience Required: 2+ Years Education: Bachelor's in IT/Engineering or related field Job Description: We are hiring 3 experienced Recruiters/Sr. Recruiters to join our dynamic team. This is a hands-on recruitment role focused on sourcing and hiring top-tier talent for cutting-edge technology positions. Key Responsibilities: End-to-end recruitment for roles in: Computer Vision, Firmware, Embedded Systems SoC, CPU/GPU, ASIC, FPGAs, RTL AR/VR, AI/ML, Deep Learning, Hardware Design Engage with candidates through various sourcing channels Screen, interview, and coordinate with hiring managers Maintain strong pipelines and ensure timely closures Key Requirements: Minimum 2 years of IT recruitment experience Strong understanding of deep tech and hardware domains Excellent communication and interpersonal skills Perks & Benefits: Benefits & Perks: 1. Incentives* 2. Monetary Awards* 3. 5-Year Retention Bonus 4. Referral Policy* 5. Internet Reimbursement* 6. Router UPS Reimbursement* 7. Term Life Insurance 8. Accidental Insurance 9. Group Medical Insurance (Family Floater) 10. On-call doctor support 11. Sodexo Benefit 13. Leave Policy 14. NPS - National Pension Scheme 15. LTA Leave Travel allowance. 16. Leave Encashment 17. Bank Assistance 18. Employee's State Insurance* 19. Gratuity 20. Provident Fund 21. Cab facility *Admissibility of the benefit may vary commensurate the department, designation, and role. How to Apply: Send your updated resume to Bharti.sharma@spectraforce.com

Become a member of one of the largest engineering companies in the world! The PSG IP and Solutions Engineering team is seeking an experienced IP Design Lead to help define and lead the next generation Transceiver solutions for PCIe, Ethernet, SmartNIC, Networking and Communications segments for programmable logic products. This forward-looking dynamic role provides unique opportunities to influence future product direction requiring a strong technical leader with strong leadership, personal communication and collaboration skills. The successful candidate will bring design solutions experience for Data Center, and/or Communications, Networking, and/or Wireless domains, ideally covering both hardware and software, with knowledge of FPGA architecture, transceiver architecture and higher level protocols. Ideally the candidate will have experience leading large design teams on strategic projects implementing designs for FPGA in networking and storage would be a distinct advantage. You will lead a complex global IP Solutions program driving various aspects of the functions including RTL design, timing closure, hardware validation etc. You will work with cross-functional teams including planning, architecture, silicon design, software and platforms to define and drive delivery of holistic customer solutions that meet market requirements and capabilities comprising silicon, soft IP, applications, SW and tools support. Manage overall program including planning, tracking, execution, executive reporting apart from getting involved hands-on in project execution. Align with global stakeholders in various sites, anticipate and mitigate risks. Qualifications: 13+ years of experience with a MS degree in IP design of complex networking, Ethernet & PCIe based IPs and subsystems. Good understanding of FPGA IP design and implementation methodology. Must have microarchitecture knowledge of PCIe, Ethernet or transceivers. In depth knowledge with Verilog, System Verilog, RTL design, FPGA design, and FPGA design tools. In depth knowledge with one of high speed serial protocols: PCIe/Ethernet. Experience in Design and verification tools: simulation tools and debug tools. End-to-end System level knowledge including design, software, firmware and hardware. Proactive, self-motivated and quick learner. Good team spirit and ability to deliver to schedule. Excellent analytical and problem-solving skills. Strong verbal and written communication skills. Ability to multi-task and work in a dynamic environment. Must have experience working closely with customers, understanding their systems and providing optimized solutions. Good communication and presentation skills a must. Should have ability to work in multi site execution and ability to influence across groups Strong experience in networking standards and protocol. Good to have programming skills (C, C++, perl, python, tcl, etc.).

Develop deep understanding of 3-D Graphics hardware pipeline, feature sets, data paths, block functionalities & interfaces . Strategize, brainstorm, and propose a DV (Design Verification) environment . Develop test bench . Own test plan . Debug all RTL artefacts . Achieve all signoff matrices . Collaborate with worldwide architecture, design, and systems teams to achieve all project goals. Required Skills & Qualifications (matching one or more profiles) Strong knowledge in developing UVM based System Verilog TBs and assertion/coverage driven verification methodologies. Strong communication skills (both written and verbal). Ability to learn, improve and deliver. Preferred Skills & Experience Inclination towards Core level verification and experience in GPU/CPU/any core level verification is a plus. Knowledge about the GPU pipeline is a plus, not mandatory. Proficiency with formal tools - working knowledge of Property based FV (Formal Verification) is a plus, not mandatory. Perl/Python scripts for automation in managing regressions, optimize run time, manage database and bug. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Qualcomm Chennai is looking for a STA and Synthesis Engineer who is passionate to work with cross-functional engineering teams. In this position, the engineer will be involved in all stages of the design and development cycles. Key Responsibilities and Skills: Synthesis, Static Timing Analysis and LEC of SoC/Cores. Full chip and block level timing closure, IO budgeting for blocks. Logical equivalence check between RTL to Netlist and Netlist to Netlist. Knowledge of low-power techniques including clock gating, power gating and MV designs. ECO timing flow. Proficient in scripting languages (TCL and Perl). Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 1-5 years of experience.

15+ years of experience in SoC design Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. 12+ years of experience with a Bachelor's/ Masters degree in Electrical/ Electronics engineering

12+ years of experience in SoC design Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. 12+ years of experience with a Bachelor's/ Masters degree in Electrical/ Electronics engineering

We are seeking highy motivated individuas with a BS, MS, or PhD degree in Computer Science, Computer Engineering/ECE, ready to hande the chaenging probems in future technoogies and designs. We are aso ooking for candidates with Strong C/C++background to ead our eading-edge agorithmswithin our EDA soutions to increase our design team’s productivity and chip quaity and performance. Our dynamic goba team is ooking to enist enthusiastic professionas to join word-cass hardware design teams responsibe for deveoping the most chaenging and compex systems in the word. We are seeking energetic, highy motivated individuas wiing to go the extra mie with the aim of heping the overa IBM deveopment team. Strong interpersona skis are needed to coordinate deiverabes and requirements from severa areas within and outside of the organization.There are many opportunities to gain and utiize a deep understanding of future issues and provide input towards decisions affecting system deveopment, ogica and physica design as we as sophisticated methodoogy directions. Individuas who are chosen to become a part of our word cass deveopment teams wi be heping advance IBM’s eadership in deveoping the highest performing computers and changing hardware soutions. Do you want to be an IBMerCome THINK with us! Required education Bacheor's Degree Preferred education Master's Degree Required technica and professiona expertise 4+ years of IT experience Strong C/C++programming skis in a Unix/Linux environment is a must. VLSI knowedge, Knowedge in front end inting toos and checkers and RTL Checkers. Great scripting skis – Per / Python/She Proven probem-soving skis and the abiity to work in a team environment are a must Preferred technica and professiona experience RTL Lint Checkers , Front end verification fow, VLSI knowedge, VHDL/Veriog, computer architecture

As a Logic Design Engineer in the IBM Systems division, you wi be responsibe for the microarchitecture design and deveopment of features to meet Secure, high performance & ow power targets of the Mainframe and / or POWER customers. Deep expertise in the impementation of functiona units within the core / cache / Memory controer / Interrupt / crypto / PCIE / DLL Additiona responsibiities: ogic (RTL) design, timing cosure, CDC anaysis etc. Understand and Design Power efficient ogic. Agie project panning and execution. Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bacheor's Degree Preferred education Master's Degree Required technica and professiona expertise Minimum 8+ years of experience in Chip design and deveopment. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, mutipiers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Veriog

As a Logic design Engineer in the IBM Systems division, you wi be responsibe for the microarchitecture design and deveopment of features to meet Secure, high performance & ow power targets of the Mainframe and / or POWER customers.Deep expertise in the impementation of functiona units within the core / cache / Memory controer / Interrupt / crypto / PCIE / DLLAdditiona responsibiities:ogic (RTL) design, timing cosure, CDC anaysis etc.Understand and Design Power efficient ogic.Agie project panning and execution.Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bacheor's Degree Preferred education Master's Degree Required technica and professiona expertise Minimum 8+ years of experience in Chip design and deveopment. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, mutipiers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Veriog

As a DFT Engineer, you will be responsible for developing and implementing Design for Test methodologies for complex VLSI designs. You will ensure the testability and manufacturability of our products by working closely with design, verification, and physical design teams, while employing state-of-the-art techniques to optimize coverage, cost, and performance. Responsibilities: 1. Develop and implement DFT architectures and strategies for complex SoC designs. 2. Insert and verify DFT features such as scan chains, Built-In Self-Test (BIST) for memory and logic, and boundary scan (IEEE 1149.1/1149.6). 3. Perform ATPG (Automatic Test Pattern Generation) and analyze coverage metrics to ensure high fault coverage. 4. Collaborate with RTL designers to ensure seamless integration of DFT features into the design. 5. Debug and resolve test-related issues in simulation, silicon validation, and production. 6. Work closely with the physical design team to implement scan and clock constraints for timing closure. 7. Optimize test time, power, and cost without compromising coverage and quality. Participate in silicon bring-up and post-silicon validation activities. 8. Generate and maintain DFT documentation, including test plans, methodologies, and results. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 2. 210 years of experience in DFT for VLSI designs. Strong knowledge of DFT methodologies, including scan insertion, BIST, and ATPG. 3. Experience with EDA tools such as Synopsys Tetramax/DFTMax, Cadence Modus, or Mentor Tessent. Proficiency in 4. Verilog/SystemVerilog and scripting languages (Python, TCL, Perl). 5. Solid understanding of STA concepts and constraints related to DFT. 6. Experience in debugging silicon and ATE test patterns. Knowledge of test standards like IEEE 1149.x (JTAG) and 1500. 7. Excellent problem-solving skills and ability to work in a collaborative environment. Preferred Qualifications: 1. Experience with low-power DFT techniques. 2. Familiarity with fault diagnosis and yield improvement methodologies. 3. Exposure to advanced nodes (7nm, 5nm, or below) and FinFET technologies. 4. Knowledge of machine learning or AI techniques for test optimization. 5. Hands-on experience with multi-core and hierarchical DFT architectures.

Role: FPGA Engineer Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in FPGA design and development, with a focus on RTL coding using Verilog or VHDL. Deep understanding of computer architecture, digital design principles, and hardware/software co-design concepts. Experience with high-frequency trading systems and ultra-low latency design techniques is highly desirable. Proficiency in FPGA development tools and workflows, such as Xilinx Vivado or Intel Quartus. Strong analytical and problem-solving skills, with the ability to optimize designs for performance, power, and resource utilization. Excellent communication and collaboration skills, with the ability to work effectively in a fast-paced, team-oriented environment.

raja.a@honeybeetechsolutions.com resume to Client Name: Proxelera Client SPOC: NA Industry: SEMICON HBTS SPOC: Shilpa Gajjala Client Req ID: ZR_116_JOB Position Name RTL Engineer Job No : PROX-14075 Position type: Permanent Total Exp: 4 to 5 years HBTS Budget: Open No of Position: 1 Notice Period: Immediate Asset: Laptop Mandatory for interview Work Location: Hyderabad Work Type: WFO Job Type: Full-time CVR Type: Internal CVR CVR Panel Name: Shilpa Gajjala Interview Rounds: 2 Rounds Interview Mode: Virtual in Teams Job Description Must have: Must Have RTL coding knowledge Must Have Top-level (SOC) level basic industry standard Arch knowledge Must Have SoC & IP level Integration knowledge Must Have IPXACT knowledge Must Have IORING and Phys & GPIOs basic functionality Must Have Design Partitioning(Tilification) knowledge Must Have Design RTL quality checks: Must Have Clock domain crossing(CDC) Must Have Reset domain crossing(RDC) Must Have LINT Must Have VSI Must Have UPF knowledge Must Have LEC(Logic equivalence check) Must Have Timing concepts & SDC knowledge Must Have Tools knowledge: Must Have Vc_static or equivalent other tools(VSI) Must Have VC_spyglass LINT, CDC and RDC Must Have 0in Must Have Formality and conformal LEC tool Must Have Design and scripting languages: Must Have Verilog and SV Must Have Perl Must Have Python Must Have TCL

#Hiring FPGA Design Engineer Exp-5- 8Years Notice Period- 0 to 15Days Location- Bangalore Job Description: RTL and FPGA design, implementation, and timing closure using Xilinx & Synopsys development tools. Bring up and validate the design in the lab and generate test reports. Perform hardware validation tasks and debug IPs. Read, understand, and modify software drivers and scripts. Skills RTL Design & FPGA Implementation: Verilog, System Verilog, Vivado , ISE, Synplify, Design Compiler FPGA Platforms: Xilinx 7-series, Ultrascale/Ultrascale+, Zynq Toolchain Expertise: Xilinx Vivado, Synopsys DC/PT, ModelSim, VCS Hardware Validation: Bitstream generation, on-board debugging, performance tuning Lab Equipment: Oscilloscopes, logic/protocol analyzers, JTAG debuggers Software & Scripting: C, C++, Python, Perl, TCL, Bash Operating Systems: Linux (device driver understanding), embedded systems Interested candidates share your resume to sreeja.s@sasnee.com ,