806 Rtl Jobs - Page 16

Role & responsibilities Please interested candidate send me cv :galeiah.g@honeybeetechsolutions.com Position Name DV Engineer -GLS Position type: Permanent Total Exp: 5-7 years Notice Period: Immediate to 15days Work Location: Bangalore KEY RESPONSIBILITIES: "Key Responsibilities: Develop and implement scalable UVM-based verification environments Lead and execute GLS (Gate-Level Simulation)timing-aware and glitch-sensitive validation is a core part of this role Perform Clock Domain Crossing (CDC) verification using industry-standard methodologies Collaborate cross-functionally with RTL, DFT, and system teams for end-to-end verification closure Analyze waveforms, root-cause issues, and contribute to debugging complex logic Requirements Required Skills: Solid hands-on experience with SystemVerilog and UVM methodologies Strong understanding and application of GLS (Gate-Level Simulation) techniques Experience with CDC verification and asynchronous domain handling Familiarity with tools such as VCS, Questa, Incisive Scripting knowledge (Python, Perl, or Shell) is a plus" AMD (Dont Share AMD Profiles) Preferred candidate profile

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. This role is based in Bengaluru. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come We make real what matters! This is your role Deploy Siemens EDA ProFPGA prototyping software and hardware solutions at customers and guide the customers to successful design bring-up Work closely with R&D to solve problems, review product specs, and find good general solutions that improve the overall product Train AE’s and customers on the solutionWin pre-sales engagements in cooperation with the technical sales teams Successfully deploy our solutions at early customer sites. This means educating the customer on best practices and tool requirements. It also means working with R&D to make the tool improvements necessary for the customer’s success. Ensure existing customers maximize the value they receive from the solution by developing and enhancing methodology that exploits the solution’s capabilities Ensure customers are kept up-to-date with the latest enhancements Provide customer requirements to R&D and marketing Work with QA and Docs to help them create tests and documentation that will improve our solutions Create examples and tutorials that are shipped with our products. Develop and/or refine methodology employed in creating and using prototypes and maximizing the value of our prototyping solution We don’t need superheroes, just super minds! A good understanding of FPGA based hardware prototyping platforms Working knowledge of multi FPGA prototyping flows(Synthesis, partitioning, PnR, runtime and debug) Practical insights into the application and usage of FPGA prototyping systems Knowledge of design mapping, testbench mapping and transactor development Expertise of hardware/software debug solutions related to FPGA prototyping Knowledge of test bench acceleration, ICE and co-model solutions Highly proficient in HDLs (Verilog/SV) for RTL design and HVLs (SV/UVM) for verification Solid background in Functional Verification, RTL synthesis and PnR flows Conversant with SoC design and architecture concepts Good communication and inter-personal skills. A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! Siemens Software. Where today meets tomorrow #LI-EDA #LI-Hybrid

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Required technical and professional expertise -2+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Responsibilities: * Develop RTL designs using Verilog, * Collaborate on ASIC projects from concept to delivery. * Ensure design compliance with industry standards. For fast response Share to mansoor@hisoltech.com

ABOUT MISTRAL: Mistrals FPGA design services include designing; building and deploying customized FPGA based solutions (Xilinx, Actel, Altera, Quicklogic, Lattice and Cypress) which integrate both custom FPGA firmware and hardware engineering. We also provide solutions on current generation FPGAs that come in three-dimensional silicon which use Stacked silicon Interconnect, leading to high density and high performance FPGAs.As an established company providing cutting-edge technologies and solutions, Mistral is committed to delivering the best FPGA and Signal Processing products and systems, meeting the unique requirements of the Aerospace and Defence industry. Location:Bangalore JOB DESCRIPTION Required Skills: Requirements Development and Test Plan Development Design architecture for FPGA based solutions. VHDL, Verilog based RTL design and Development VHDL, Verilog based Verification and Validation Digital Signal Processing algorithms experience is appreciated. Knowledge of Xilinx ISE, Vivado and Altera Quartus Tool chain Should have worked on PCIe, Aurora, JESD, DDR4, DDR3, Gig Ethernet and 10G Ethernet based design experience Have worked on Microblaze, PPC or ARM SoC(MPSoC, RFSoC,Agilex etc) based FPGA projects Mandatory Skills: RTL, DDR4, DDR3, Digital Signal Processing, ARM SOC, JESD, Ethernet, Aurora.

Very good knowledge of DFT RTL insertion including MBIST and SRAM repair Job Description In your new role you will: Drive and manage as technical member of a self contained DFT team which is responsible of: The DFT implementation of latest Infineon microcontroller products Scan insertion , ATPG, LBIST and MBIST Verification of the DFT implementation and Test pattern delivery for production testing Support the Silicon bringup activities to guarantee highest stability of the test pattern Contribute to the overall microcontroller DFT methodology Coordination of DFT workpackage s and hands-on work, status reporting Interfacing with project management, layout team and test engineering Your Profile You are best equipped for this task if you have: At least 6+ years of experience in DFT of highly complex SoCs A university degree in Electrical Engineering, Microelectronics, Physics or a similar field. Profound knowledge about semiconductor products. Expert Knowledge of DFT methods for state-of-the-art MPU/MCU products. Working knowledge of test concept or DFT concept definition. Strong track record of scan insertion and ATPG Very good knowledge of DFT RTL insertion including MBIST and SRAM repair Experience of debugging test pattern issues Programming or scripting experience Very good soft skills and experience in leading Contact: swati.gupta@infineon.com We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Learn more about our various contact channels. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

Very good knowledge of DFT RTL insertion including MBIST and SRAM repair Job Description In your new role you will: The DFT implementation of latest Infineon microcontroller products Scan insertion, ATPG, LBIST and MBIST Verification of the DFT implementation and Test pattern delivery for production testing Support the Silicon bring up activities to guarantee highest stability of the test pattern Contribute to the overall microcontroller DFT methodology Coordination of DFT work packages and hands-on work, status reporting Interfacing with project management, layout team and test engineering Your Profile You are best equipped for this task if you have: At least 3+ years of experience in DFT of highly complex SoCs A university degree in Electrical Engineering, Microelectronics, Physics or a similar field. Profound knowledge about semiconductor products. Expert Knowledge of DFT method s for state-of-the-art MPU/MCU products. Working knowledge of test concept or DFT concept definition. Strong track record of scan insertion and ATPG Very good knowledge of DFT RTL insertion including MBIST and SRAM repair Experience of debugging test pattern issues Programming or scripting experience Very good soft skills and experience in leading Contact: swati.gupta@infineon.com We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Learn more about our various contact channels. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web-scale and service provider networks. Cisco's silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus (with an on-site gym, healthcare, caf, social interest groups, and philanthropy) with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Write micro-architecture specifications and participate in reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integration and timing methodology/analysis. Develop and analyze functional coverage. Help define, evolve, and support our design methodology. Collaborate with the verification team to address design bugs and close code coverage. Work closely with the physical design team to close design timing and place-and-route issues. Triage, debug, and root cause simulation, software bring-up, and customer failures Perform diagnostic and post-silicon validation tests in the lab Minimum Qualifications: Bachelor's Degree / Master's Degreein Electrical or Computer Engineering with 7+ years of ASIC design. Prior experience working with Verilog or System Verilog programming skills Experience with simulators/synthesis/static timing constraints and related tools (e.g., VCS, DC, PrimeTime) Experience with debugging and verification methodologies Preferred Qualifications: Understanding of Networking technologies and concepts Scripting experience (Python, Perl, TCL, shell programming) Experience with formal verification tools Experience with emulation

Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Your Impact Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies. The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship. Minimum Qualifications: Bachelor's or a Masters Degree in Electrical or Computer Engineering required with at least 7+ years of experience. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Background with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Background with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Prior experience working with Gate level simulation, debugging with VCS and other simulators. Prior experience with Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 Prior experience with Scripting skills: Tcl, Python/Perl. Preferred Qualifications: Verilog design experience developing custom DFT logic & IP integration; familiarity with functional verification DFT CAD development Test Architecture, Methodology and Infrastructure Background in Test Static Timing Analysis Past experience with Post silicon validation using DFT patterns.

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Develop System Verilog/UVM-based testbenches for block-level and system-level verification. Write and execute UVM test cases to verify functional correctness of RTL designs. Perform detailed functional coverage and code coverage analysis, and drive coverage closure. Debug simulation failures, root-cause issues, and work closely with design and verification teams for resolution. Collaborate with cross-functional teams to ensure successful verification closure within project timelines. * Develop and maintain scripts using Python or other scripting languages for automation, regression management, and data analysis (optional but preferred). Apply working knowledge of standard bus protocols such as AXI, APB, UART, and IJTAG for testbench development and debugging. Document verification plans, test specifications, test reports, and maintain traceability. Skills Must have 4-6y exp SV / UVM Test bench development and test cases coding Code and Functional coverage analysis and closure Work with team for verification closure Bus protocols AXI / APB / UART/ IJTAG protocol working knowledge is an advantage. Nice to have Experience with python or any other scripting language is a plus

Responsibilities: * Develop RTL designs using Verilog, Synthesis with SpyGlass & LINT checks. * Collaborate on ASIC projects from concept to delivery. * Ensure design compliance with industry standards. Apply & Share to mansoor@hisoltech.com

Looking for Siemens EDA ambassadorsLead Software Engineer for Product Validation and Customer support for PowerPro We are passionate about innovations that mean real progress, and we are curious about technologies that still need to be developed. Do you want to use curiosity, passion, and creativity to make the lives of millions of people easier and betterJoin us – whichever path you take, we’re looking forward to seeing your point of view! As an integral part of the Siemens EDA team, you will contribute to Siemens EDA by growing efficiency and customer satisfaction Siemens EDA’s Power platform. This is an ambitious position that will assist in growing Siemens's EDA business in India. About the group: We are in DDCP (Digital Design Creation Platform group) which include top industry tools like Tessent, PowerPro, Catapult, Aprisa. We are part of DPRS (Devops, Product, Release & Support group) inside DDCP which works on cutting edge tools like PowerPro. Our team is responsible for Product Validation, Customer Support & Release work for PowerPro tool. PowerPro is the commercially available RTL sequential power optimization and power analysis tool. We are a team driven with lots of energy, synergy and passion. Job Responsibilities: Work as an integral part of Product Validation and Customer Support team to validate and educate feature of PowerPro. Being the internal end-user of the tool, validate all features and report issues. Development of test plan and writing test cases. Take measures to improve quality of Product and test environment. Support and debug customer test design methodologies using our products. Participate in architecture reviews and involve in defining features prototyping. Get along with field teams to understand customer design flows requirements and propose measures to optimize and improve flow results. Analyse customer reported bugs and plug gaps in testing, incorporate newer designs/flows. Use technical expertise to respond to customer inquiries, demonstrate products. Provide field application support to customer. Role may involve interaction with customers on critical issues to narrow down the problem. Lead 1-2 junior folks or Intern. guide them and help them in day-to-day activities. Technical Skills (Must have): B.Tech (EE/ECE) or M.Tech (VLSI/Microelectronics) with working experience of 5+ Years. Good knowledge of ASIC design flows, Verification, Digital Logic, Synthesis, HDL Languages Verilog/VHDL/SV. Good understanding of low-power SOC design principles. Experience with class of products like simulation, synthesis, Place & Route, etc. Excellent problem-solving and debugging capability. Technical Skills (Good to have): Low Power concepts, RTL/Gate Simulation and Emulation, SPEF, Different tech nodes. Knowledge of one of the scripting languages like Perl, Tcl. Python will be a plus. Worked on designs to apply power solutions, UPF etc. Different Tool knowledge like Power Artist, Joules, Prime Power/PTPX, Questa, VCLP, DC etc. Worked in EDA CAD team for RTL Soft Skills: Excellent verbal and written communication skills. Self-starter, motivated and strong teammate. Team Contributor, Quick learner. Hard working, sincere and committed to work. Team leader We’ve got quite a lot to offer. How about you A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! Transform the everyday Accelerate transformation #li-eda #li- Hybrid

Develop Detailed Documentation for Verification Strategy and Test Plan for IP, Subsystem and SoC. Directed and Random Verification at IP, Subsystem and SoC Level for complex ARM / RISC-V processor based MCU, MPU products, Mixed Signal SoCs, Processors, Memory Subsystems, Connectivity Platforms, Analog, Security Acceleration, General Peripherals. Perform Functional and Code Coverage Analysis. Experience and Skills Required 5 to 15 years of experience in IP SoC Verification. Expertise in Verilog, System Verilog, UVM, Constrained Random Verification, Formal Verification, Mixed Signal Verification, Post-Layout Gate Level Simulations, Code Coverage and Functional Coverage analysis. Development of Verification IP and Testbenches. Experience with AMS simulations desired. Must have strong debug and analytical capabilities, root cause analysis. In-depth understanding of SoC Design Flow, RTL Implementation, Analog Circuit models. Soft Skills Strong analytical, problem-solving, and hands-on skills. Self-driven and thrives when facing open-ended tasks. Start-up mentality: fast-paced, flexible and team-oriented. Good written and verbal communication skills with great documentation skills. Flexibility to work with varied schedules and tolerance for ambiguity.

Front End Integration of Digital, Analog IPs and Subsystems to build complete SoC Netlist. IOMUX and Padring generation and integration. Design of SoC Specific Logic IPs. Perform quality checks like Lint and CDC at SoC level. Implement all feedback from Verification and Physical Design teams for all changes required. Develop SoC level Testbench for RTL and Postlayout Simulations. Collaborate with ATE and Test teams and deliver test patterns for Probe and Package level testing. Support Verification and Post-Silicon Debugging of issues. Experience and Skills Required 10-15 Years Experience in front end integration for complex SoCs. Strong scripting skills. Hands on experience in RTL coding, Lint, CDC. Experience in developing IOMUX and Padring. Expertise in developing testbench for SoC to support directed and random verification. Experienced with working with ATE teams for delivery of test patterns. Soft Skills Strong analytical, problem-solving, and hands-on skills. Self-driven and thrives when facing open-ended tasks. Start-up mentality: fast-paced, flexible and team-oriented. Good written and verbal communication skills with great documentation skills. Flexibility to work with varied schedules and tolerance for ambiguity.

Role & responsibilities: Extensive hands on and teaching experience on Digital / SV /UVM/ Verilog / VHDL /DFT tools Extensive experience in Back-end design Experience on Mentor Graphics EDA flow is an added advantage Responsible for development and support of Projects. Responsible for Debugging the source codes in Verilog, SV, and UVM. Responsible for Training Delivery and Support Preferred candidate profile Sound Knowledge on Digital / Verilog / VHDL / SV / UVM / DFT / Back-end design 3 to 8 years industry/teaching experience Good communication & presentation skill

Skills required: 1. Should have worked on USRP N310/X310 (N3xx/X3x0) 2. In-depth Knowledge of FPGA Architecture 3. Able to write own RTL custom HDL or drops in IP a) VHDL, Verilog, System,Verilog, Vivado HLS b) Xilinx IP, Vivado Block Diagram 4. Should have developed RFNoC Block 5. Have working knowledge of USRP Hardware Driver (UHD) 6. Able to write custom FPGA logic in RFNoC Blocks 7. Able to use library of existing RFNoC Blocks a) FFT, FIR, Signal Generator, Fosphor 8. Have understanding of GNU Radio interface to RFNoC Block 9. FPGA debugging and HW/SW integration 10. Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed 11. In-depth knowledge of XILINX ZYNQ 71xx/pl-kINTEX-7 based RFNoC architecture is must. 12.Understand Customer requirements, define architecture and detailed design 13. Good Customer Communication Skills 14. Working knowledge of Agile

In-depth Knowledge of FPGA Architecture Able to write own RTL custom HDL or drops in IP VHDL, Verilog, System,Verilog, Vivado HLS Xilinx IP, Vivado Block Diagram

Who We Are The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Who You'll Work With You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in Bangalore India with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies. The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship. Who You Are You are an ASIC Design for Test Hardware Engineer with 10+ years of related work experience with a broad mix of technologies. Minimum Qualifications: Bachelor's or a Masters Degree in Electrical or Computer Engineering required with at least 10 years of experience. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Experience working with Gate level simulation, debugging with VCS and other simulators. Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 Strong verbal skills and ability to thrive in a multifaceted environment Scripting skills: Tcl, Python/Perl. Preferred Skills: Verilog design experience developing custom DFT logic & IP integration; familiarity with functional verification DFT CAD development Test Architecture, Methodology and Infrastructure Test Static Timing Analysis Post silicon validation using DFT patterns. Why Cisco #WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all. We embrace digital, and help our customers implement change in their digital businesses. Some may think were "old" (36 years strong) and only about hardware, but were also a software company. And a security company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do - you cant put us in a box! But "Digital Transformation" is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it). Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take difference to heart. Because without diversity of thought and a dedication to equality for all, there is no moving forward. So, you have colorful hair Dont care. Tattoos Show off your ink. Like polka dots Thats cool. Pop culture geek Many of us are. Passion for technology and world changing Be you, with us!,

Position: Digital Head Semiconductor BU (Confidential Search) Location: Hyderabad / Chennai/Bangalore We are partnering on a confidential leadership mandate for a Digital Head to drive digital strategy, delivery excellence, and innovation across global semiconductor programs. Key Responsibilities: Lead and grow multi-disciplinary teams Semiconductor Digital Design (RTL, PD, DV, DFT) Own delivery of complex SoC/ASIC programs across global accounts Define capability roadmap, drive innovation in AI/ML + EDA Partner with sales, pre-sales, and engineering to shape go-to-market Ideal Profile: 15 to 25 years in semiconductor design, with 5+ years in senior leadership B.E./B.Tech in ECE/VLSI; M.Tech/MS preferred with 20+ years of experience Proven track record in RTL, DV, DFT, and EDA toolchains Must have Leadership experience Candidates currently or previously working in these companies would likely have relevant experience) Semiconductor Product/Design Companies: Engineering Services/Design Services Companies: EDA & IP Companies If you meet 80% of the requirement contact : bdm@intellisearchonline.net M 9341626895(whatsapp) Role & responsibilities

Minimum qualifications: Bachelor s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience. 15 years of experience in ASIC RTL design. Experience with RTL design using Verilog/System Verilog and microarchitecture. Experience with ARM-based SoCs, interconnects and ASIC methodology. Preferred qualifications: Master s degree in Electrical Engineering or Computer Engineering. Experience driving multi-generational roadmap for IP development. Experience leading interconnect IP design team for low power SoCs. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology. Responsibilities Lead a team of people to deliver fabric interconnect design. Develop and refine RTL design to aim power, performance, area, and timing goals. Define details such as interface protocol, block diagram, data flow, pipelines, etc. Oversee RTL development, debug functional/performance simulations. Communicate and work with multi-disciplined and multi-site teams.

Minimum qualifications: Bachelor s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience. 15 years of experience in ASIC RTL design integration. Experience in Verilog or Systemverilog coding. Experience in High performance design, Multi power domains with clocking of multiple SoCs with silicon. Preferred qualifications: Master s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience. Experience with ASIC design methodologies for front quality checks including Lint, CDC/RDC, Synthesis, DFT ATPG/Memory BIST, UPF and Low Power Optimization/Estimation. Experience with chip design flow and understanding of cross domain involving DV DFT/Physical Design/software. Knowledge in one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Lead a team of ASIC RTL engineers on Sub-system and chip-level Integration activities including planning tasks, hold code and design reviews, code development of features. Interact closely with architecture team and develop implementation (microarchitecture and coding) strategies to meet quality, schedule and PPA for Sub-system/chip-level integration. Work closely with the cross-functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process.

Minimum qualifications: Bachelor s degree in Electrical/Computer Engineering or equivalent practical experience. 2 years of experience with RTL design using Verilog/System Verilog and microarchitecture. Experience in ARM-based SoCs, interconnects and ASIC methodology. Preferred qualifications: Master s degree in Electrical/Computer Engineering. Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC). Experience with methodologies for low power estimation, timing closure, synthesis. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As part of our platform IP team, you will be a part of a team that designs foundation and chassis IPs (NoC, Clock, Debug, IPC, MMU and other peripherals) for Pixel SoCs. You will collaborate with members of architecture, software, verification, power, timing, synthesis, etc. to specify and deliver quality RTL. You will solve technical problems with innovative micro-architecture, low power design methodology and evaluate design options with complexity, performance and power. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc. Perform RTL development (SystemVerilog), debug functional/performance simulations. Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks. Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up. Communicate and work with multi-disciplined and multi-site teams.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: GPU Design and micro-Architect who will work across functions like GPU architecture and Systems in design and micro-architecture of the next generation GPU features. Work very closely with Architecture teams to come up with micro-architecture and hardware specification for features Design and RTL ownership Work very closely with Design Verification teams to review test plans and sign off the validation of all design features across products Work closely with physical design teams to achieve the right power, performance and area metrics for the GPU blocks Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Successful candidates will have strong coding skills and a desire to learn full stack development, including but not limited to Feature Development, Testing and Customer Support. Candidates should also be comfortable working as part of a global team and possess good verbal & written communication skills. A successful individual for this role should possess A successful individual for this role should possess: * Good knowledge of cloud technologies including networking and security * Excellent Development skills in UI and good knowledge in JavaScript, React.js, Jest, RTL, Cypress etc. following user experience & visual design principles having responsive & adaptive design. * Good Development skills in Golang to deliver robust and scalable solutions. * A strong technical background in using development tools such as Git, VS Code, make etc. * Strong analytical and problem-solving expertise, with the ability to investigate issues and apply fixes throughout the development lifecycle. * Experience in applying Cloud Engineering practices to enable Continuous Delivery. * Ability to take ownership of tasks, proactively driving them to their completion. * Automation skills in testing, scripting (e.g. Bash), pipelines, and utilities. * Experience in monitoring and alerting. * An understanding of fundamental Security and Privacy principles. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise * 6-9 years experience in Software development and Full stack development. * Technical expertise in building, deploying and running applications in a Cloud environment such as AWS. * Strong proficiency with Kubernetes/OpenShift and container orchestration. * Familiarity with Docker, Istio, and other container technologies. * Development skills in UI and good knowledge in JavaScript, React.js, Jest, RTL, Cypress etc. following user experience & visual design principles having responsive & adaptive design. * Development skills in Golang to deliver robust and scalable solutions. * Management of version control and collaboration using Git and GitHub. * Strong scripting experience, e.g. bash. * Experience in utilizing Helm charts for packaging and deploying containerized applications. * Ability to implement and maintain Git Ops workflows using Flux CD/Argo CD. * Knowledge of Terraform to provision and manage infrastructure. * Experience in applying secure development practices. Preferred technical and professional experience * 6+ years experience in cloud engineering, Golang, Docker/Kubernetes/OpenShift, JavaScript, React.js, RTL, Jest, Cypress etc. * Proficient in agile development methodologies and tools * Prior experience of managing Security and Privacy controls in a Cloud environment such as AWS.

Key Responsibilities: Define and lead the strategy for VLSI front-end design services Build and scale high-performing VLSI engineering teams (from 50 to 500+) Engage with customer design managers and secure design wins through deep technical collaboration Mentor and upskill engineering teams in line with evolving industry needs Ensure successful delivery of ASIC design and verification projects Develop innovative proposals and drive new project wins Collaborate with internal resourcing teams and external partners to fulfill staffing needs Represent VLSI practice in industry forums and events Must-Have Skills: Strong leadership experience in VLSI/ASIC front-end engineering Expertise in RTL design, UVM-based verification, UPF/SDC, formal verification, emulation Hands-on with commercial EDA tools (Synopsys, Cadence, Siemens) Familiarity with Verilog and standard formats (LEF/DEF/SPEF) Client engagement, delivery management, and proposal leadership Good-to-Have Skills: Industry connects with EDA vendors, foundries, and Tier-1 semiconductor companies Knowledge of ASIC-package co-design Experience in defining VLSI roadmaps, SoW/MSA processes Automation exposure (Python/Perl) Awareness of semiconductor industry trends and competitor insights