1147 Rtl Jobs - Page 12

About The Role This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; About The Role - Grade Specific Focus on Electrical, Electronics and Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in ...

The Client DDRPHY team is looking for an energetic and passionate Logic Design Engineer who will work on high-speed digital design targeted towards low power optimized IP implementations. You will be responsible for overseeing definition, design, verification and your responsibilities will include but are not limited to - defining architecture and microarchitecture features of the block being designed, implementing RTL in System Verilog, setting up Automation flows for IP Logic Design, ensuring RTL quality via Front End tools like Lint, CDC, VCLP, Synthesis QA checks etc, creating FE packages for IP milestones that meet SoC Collateral requirements, create innovative automated solutions to he...

Formal Verification Engineer Job Title: Formal Verification Engineer Experience: 2-6 years Education: B.E/B.Tech/M.Tech in ECE/EE Responsibilities: Apply formal methods to verify safety-critical logic Write properties and assertions using SVA Use formal tools (JasperGold, VC Formal, etc.) Collaborate with RTL and functional teams for equivalence checks Requirements: Experience with formal verification tools Strong debugging and abstraction skills Understanding of property specification and protocol checking

RTL Verification Engineer Job Title: RTL Verification Engineer Experience: 0-3 years Education: B.E/B.Tech/M.Tech in ECE or related field Responsibilities: Develop testbenches in System Verilog Write and execute testcases for RTL validation Perform code coverage and functional coverage analysis Debug simulation failures and regressions Requirements: Good knowledge of Verilog/System Verilog Basic understanding of UVM and testbench architecture Experience with simulation tools like VCS or Questa

STA Engineer Job Title: STA (Static Timing Analysis) Engineer Experience: 2-5 years Education: B.Tech/M.Tech in ECE Responsibilities: Perform timing analysis and closure using Prime Time or Tempus Work with RTL, synthesis, and PnR teams to fix timing issues Define and debug timing constraints (SDC) Analyse timing corners, ECOs, and sign-off checks Requirements: Strong understanding of timing concepts (setup, hold, skew, etc.) Experience with timing tools and constraints debugging Familiar with multi-voltage/multi-mode designs

Responsible for high-performance microprocessor blocks RTL to GDSII implementation Perform block-level synthesis, floor-planning, placement, and routing. Close the design to meet timing, power budget, and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8-12 years of industry experience in physical design methodology. Good knowledge and hands-on experience in physical design methodology, which includes logic synthesis, placement, clock tree synthesis, and routing. Should be knowledgeable ...

Develop and maintain formal equivalence checking flows using Synopsys Formality. Collaborate with cross-functional teams to align verification methodology with design goals. Implement and support Formality ECO flows for incremental synthesis. Drive methodology improvements for SoC design verification. Coordinate with internal stakeholders and external vendors to deliver high-quality solutions. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Bachelor’s or Master’s degree in Computer Science, Electronics Engineering, or VLSI Design. 5–8 years of hands-on experience with Synopsys Formality or similar tools (e.g., Cadence Con...

Digital Design Engineer Job Title: Digital Design Engineer Experience: 0- 3 years Education: B.E/B.Tech/M.Tech in ECE, VLSI Responsibilities: Design and implement combinational and sequential logic Create synthesizable RTL for custom digital blocks Optimize designs for area, power, and performance Work with validation and test teams for post-silicon debug Requirements: Solid understanding of digital design principles Knowledge of finite state machines, timing, pipelining Basic exposure to FPGA or ASIC flows , DACs, PLLs, LDOs, bandgap references Perform schematic entry, simulations, and layout reviews Ensure proper matching, noise, and layout parasitic handling Work closely with layout and m...

ASIC Design Engineer Job Title: ASIC Design Engineer Experience: 14 years Education: B.E/B.Tech or M.Tech in EE, ECE, VLSI Responsibilities: Design RTL for ASIC blocks/IPs Perform logic synthesis and DFT insertion Work with verification and backend teams to close timing and area Debug issues in simulation, synthesis, and STA stages Ensure design complies with low power and clock domain constraints Requirements: Good knowledge of RTL coding, clock gating, and synthesis constraints Hands-on with Synopsys or Cadence design tools Familiarity with ASIC design flow

Role Overview: You will be responsible for leading Emulation & FPGA prototyping and verification for complex SoCs/ASICs. This role will involve RTL/testbench development, lab bring-up, debugging, and close collaboration with design, software, and verification teams to ensure robust pre-silicon validation and hardware-software integration. Key Responsibilities: - Develop and implement verification strategies using Emulation & FPGA prototyping platforms. - Create and maintain RTL/testbenches aligned with ASIC designs. - Lead lab bring-up, debug HW/SW interactions (JTAG, UART, analyzers). - Collaborate with software/ASIC teams for seamless integration and firmware readiness. - Design architectu...

Role Overview: The ideal candidate for this role should possess a Bachelor's or Master's degree or equivalent practical experience along with a minimum of 5 years of experience in Design for Testability/Design for Debugging (DFT/DFD) flows and methodologies. You should have a proven track record in developing DFT specifications and DFT architecture, fault modeling, test standards, and industry DFT/DFD/Automatic Test Pattern Generation (ATPG) tools with Application-Specific Integrated Circuit (ASIC) DFT, synthesis, simulation, and verification flow. Key Responsibilities: - Experience with DFT for a subsystem with multiple physical partitions - Familiarity with Internal JTAG (IJTAG) ICL, Proce...

You will be joining Broadcom Central Engineering team as a Multi Skilled RTL, Verification engineer with DFT expertise. You will have the opportunity to work in domains such as RTL, Verification, and DFT for Complex Memory, IO subsystems, and Hierarchical Blocks including BIST. This role offers a great opportunity for individuals who are eager to deepen their knowledge in end-to-end Chip development flow with specialized expertise in DFT and Memory BIST, eBIST. **Key Responsibilities:** - Perform RTL development and Verification for Digital subsystems, Memory Subsystems including BIST. - Execute DFT Insertion and Verification signoff for IO, ARM-PNR, Memory Digital Subsystems utilizing Tesse...

As Logic deisgn engineer for Power Management, you will be responsible for design and development of power management and sustainability features for high performance Processors chips. 1. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions 2. Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature 3. Guide junior engineers. Represent as Power engineer in various forums. 4. Signoff the Pre-silicon Design that meets all the functional, area and timing goals 5. Participate in silicon bring-up and validation of the hardwar 6....

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC ver...

Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify designs or repair eq...

Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify designs or repair eq...

Long Description 1. ASIC RTL Engineer : RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet - Any One I2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One scripting languages like Make flow, Perl ,shell, python - Any One LocationBangalore / Hyderabad / Kochi Experience - 7+ - Lead/Architect 2. Emulation Lead JD - Emulation Lead (Zebu/ HAPS /Veloce/Palladium and Module Build (End to End) Location - Bangalore / Hyderabad Experience - 7+ - Lead/Architect 3. Lead Design Verification Engineer : 7+ years of hands-on DV experience in SystemVerilog/UVM. Must be able to own and drive the verification of a block / s...

Compiler development for converting SNORT rule set to state table, Regex look up in conjunction with FPGA based acceleration and result processing C++/C based compiler design and development Strong communication skills to interact with the customer,

FPGA design & development with expertise in MATLAB model-based design, real-time DSP on Xilinx, Vivado/Vitis flows, HDL (VHDL/Verilog), FPGA architecture, high-speed interfaces, real-time processing, and strong debugging skills.

Key Responsibilities: Develop, integrate, and validate RTL designs for complex ASIC/SoC projects. Perform lint checks, CDC analysis, and RDC verification using industry-standard tools (Spyglass, Meridian, etc.). Collaborate with design verification teams to ensure functional correctness and quality sign-off. Drive synthesis-friendly RTL coding practices and participate in design reviews. Debug and resolve issues across RTL, lint, CDC, and timing. Work closely with architecture and verification teams for spec-to-RTL implementation . Required Skills & Expertise: 5+ years of experience in ASIC RTL design & verification . Strong hands-on expertise in Lint, CDC, and Meridian tools. Proficiency in...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Job Description Responsibilities: STA setup, convergence, reviews and signoff for multi-mo...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Description This position is for RTL designer role in DSP processor team. The position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the challenges posed by advanced technologies. The successful candidate will possess detailed understanding of RTL design, synthesis, static timing analysis, formal verification, PLDRC, clock domain crossing, and low power techniques. Knowledge and experience of microprocessor integration is a definite advantage. Skills/Experience Must have 3 to 15 years of practical experience with details of RTL development (VHDL and/or Verilog) including:...

Role Overview: As a member of the Common Hardware Group (CHG) at Cisco, you will be part of a team that delivers cutting-edge silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. Your work will involve designing networking hardware for Enterprises, Service Providers, Public Sector, and Non-Profit Organizations worldwide. Join the team in shaping Cisco's groundbreaking solutions by participating in the design, development, and testing of advanced ASICs that are at the forefront of the industry. Key Responsibilities: - Implement Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics requirements of the des...

As a Senior DFT Engineer at Samsung Semiconductor India Research (SSIR), you will play a crucial role in full chip DFT architecture, implementation, timing closure, and post-silicon validation. Your responsibilities will include: - Planning scan architecture and optimization for pattern volume - Performing pin mixing and scan compression planning - Implementing power optimization techniques in test modes - Planning MBIST architecture and insertion - Verifying analog and mixed signal IP testing architecture You will also be responsible for tasks such as timing closure of scan and MBIST, writing SDCs, debugging timing issues, and interpreting tester results. Additionally, you will need to unde...

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: We are seeking a highly skilled and experienced Debug IP Design Engineer/Microarchitect to focus on the development of Debug IPs. The ideal candidate will have a strong background in IP design, verification, and delivery, with specific expertise in CoreSight IP design. Key Responsibilities: Debug IP Design: Focus on the design and development of CoreSight based Debug IPs, ensuring they meet the required specifications and performance standards. RTL Design: Utilize your experience in RTL design for complex SoC development using Verilog and/or SystemVerilog to create efficient and reliable IPs. Arm-Based Desi...