You are best equipped for this task if you have: Should have experience of 5 years Strong Low Power Concepts including UPF IEEE format and constructs. Debug skills required on Synthesis run issues like : RTL not synthesizable, UPF, constraints related impact on Synthesis, Logical Equivalence Checking , Abort resolutions and Non Equivalence Debugging skills. Good to have Physical aware synthesis knowledge , LEF/DEF formats, basics of synthesis should be strong.

We are seeking highly motivated, energetic, and team-oriented individual contributors who can work on synthesis, LEC, and constraints for NXPs digital IPs, working in close collaboration with the RTL team. Key Responsibilities Work closely with the architects and RTL team on synthesis, LEC, and constraints of NXP digital IPs Carry out floor planning, and physically aware synthesis on high-performance IPs Perform timing and power analysis on the design database (db), improve the recipe, and provide timing feedback to the RTL team Leads or solo owners are expected to work with minimal micro-management needs. They should be able to communicate with other project members to manage task divisions and deliveries Responsible for delivering the weekly status with desired metrics information Key Technical Skills Self-starter with 312 years of relevant experience in synthesis, LEC, and constraints at the IP level. Candidate should be able to set up the synthesis and LEC flows from scratch Strong fundamentals of synthesis and place & route (P&R) Good scripting knowledge (TCL, Perl, Python) Knowledge of Fusion Compiler, Genus/Innovus, and Primetime

In this role you will work on SoC/Sub-system level Emulation model development and design bring up on Zebu/Veloce HW platforms. Additionally, you will work closely with design, verification, validation, and SW teams to implement emulation testbench (XTORs, Speed Adaptors) and features required to develop content on emulation models. You would develop tests to qualify models. Key Skills 8-15 years of experience on SoC/Sub-system Emulation of multi-million gate and complex design with multiple clocks and power domains Experience in microcontroller architecture, Cores ARM A/M series, Interconnect (NIC, FlexNoC), Protocols like AHB, AXI, Memory (Flash, SRAM, DDR4/5), and memory controllers Experience in automotive protocols like LIN, CAN, high-speed protocols like PCIe, Ethernet, USB etc. would be an advantage Emulation model creation from RTL/Netlist Experienced in Zebu/Veloce emulation platforms Create and execute test plans targeting emulation model qualification Experience with Speed Bridge Integration and perform real-time testing would be a plus Experience in integrating Acceleration VIPs/XTORs and perform co-emulation Scripting and Automation to continuously improve operational efficiency.

About the Role We are seeking a highly skilled and experienced Hardware Architect to join our dynamic team. The ideal candidate will have a strong background in hardware architecture, particularly in writing architectural models and conducting performance and power analysis of chips. In addition to collaborating closely with our hardware team, the successful candidate will also work with our software department, which focuses on compilers, runtime software, and kernel software, to ensure cohesive and efficient chip design and functionality. This is what you are responsible for Architecture Modeling: Develop architecture models for AI chips. Collaborate with cross-functional teams to ensure models accurately reflect design specifications and requirements. Utilize industry-standard tools and methodologies for architecture modeling. Performance Analysis: Conduct in-depth performance analysis to identify and resolve bottlenecks in AI chip designs. Use simulation and analytical methods to predict and enhance chip performance. Work with software teams to validate performance models with real-world applications and workloads. Power Analysis: Perform detailed power analysis to ensure AI chips meet stringent power consumption targets. Necessary Qualifications: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field Minimum of 8 years of experience in hardware architecture/design of silicon chips Strong understanding of computer architecture principles and AI chip design. Proficiency in C/C++/Verilog. Define micro-architecture and write detailed design specifications. Implement complex digital functions and algorithms in RTL. Experience with synthesis, static timing analysis, and linting tools. Experience in any of processor subsystem design, interconnect design, high speed IO interface design.

We are seeking an exceptional Senior ASIC Verification Engineer to join our innovative semiconductor team. You will lead verification initiatives for complex ASIC designs and drive technical excellence across projects. About the Role : You will be responsible for developing advanced verification environments, leading cross-functional technical initiatives, and mentoring team members while ensuring the highest quality standards in our ASIC designs. What You'll Do : - Design and implement advanced System Verilog/UVM verification infrastructures - Lead verification planning and execution for complex ASIC projects - Develop comprehensive test strategies ensuring thorough design validation - Drive debug resolution through collaboration with cross-functional teams - Mentor and provide technical guidance to verification team members - Enhance and optimize verification methodologies - Own end-to-end SOC verification environments Required Skills & Experience : - BS/MS in Electrical/Computer Engineering - 2+ years of hands-on ASIC verification experience - Expert-level SystemVerilog, UVM, and object-oriented programming skills - Strong proficiency with industry tools like VCS, Xcelium, QuestaSim - Advanced debugging and problem-solving capabilities - Excellent communication and collaboration abilities - CLP and GLS - Python/Perl scripting expertise Nice to Have : - Experience with PCIe, DDR, USB, C2C - Knowledge of on-chip interconnects and processor subsystems - Background in formal verification methods - Prior experience on Emulators

What You'll Be Doing : - In this position, you will expect to lead all block/chip level PD activities. - PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification. - Work in collaboration with design team for addressing design challenges. - Help team members in debugging tool/design related issues. - Constantly look for improvement in RTL2GDS flow to improve PPA. - Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. - Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets. Minimum Qualifications : - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. What We Need To See : - Strong experience in Physical Design. - Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure. - Expertise on high frequency design methodologies. Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Working experience with tools like ICC2/Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation. - Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred. - Well versed with timing constraints, STA and timing closure. - Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools. - Ability to multi-task and flexibility to work in global environment. - Good communication skills and strong motivation, Strong analytical & Problem solving skills. - Proficiency using Perl, Tcl, Make scripting is preferred. - Widely considered to be one of the technology worlds most desirable employers, offers highly competitive salaries and a comprehensive benefits package. Require candidates with a minimum of 5 years of relevant experience

Skills: Programming Language : Strong in VHDL along with Working knowledge on Verilog/System-Verilog Preferable Skills: * Use of tools such as Quartus, Vivado, Libero and their IPs * Experience with using any simulator (Modelsim, XSIM, etc.) * Deep understanding of FPGA design flow including RTL design, verification, logic synthesis, timing analysis, floor-planning, ECO, bring-up & lab debug. * Experience with gate-level understanding of RTL and synthesis * Experience with basic lab equipment such as Logic analyzers, scopes, protocol analyzers, etc. * Development experience and board level debugging on Ethernet (1G, 10G) experience is preferable * Experience in DDR3/DDR4 is preferable * Experience in AMBA/AXI is preferable * Good interpersonal and communication skills Vhdl

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 4years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging RTL code using simulation tools Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred.

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 4years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging RTL code using simulation tools Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Principal Duties and Responsibilities: 12+ Years of Experience in Logic design /micro-architecture / RTL coding Must have hands on experience with SoC design, synthesis and timing analysis for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Work closely with the SoC DFT, Physical Design and STA teams Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as DesignCompiler, Genus, FusionCompiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Required Qualifications Bachelor's degree /master"™s degree in Electronics & Tele Engineering, Microelectronics, Computer Science, or related field. 9+ years RTL Design/Hardware Engineering experience or related work experience. Skills/Experience Required Strong Domain Knowledge on RTL Design , implementation, and integration. Experience with RTL coding using Verilog/VHDL/System Verilog. Experience in micro-architecture & designing cores and ASICs. Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc. Exposure in scripting (Pearl/Python/TCL). Strong debugging capabilities at simulation, emulation, and Silicon environments. Collaborate closely with cross-function team located in different time zone to research, design and implement performance and power management strategy for product roadmap. Good team player. Need to interact with the other teams/verification engineers proactively. Responsibilities Design and lead all Front-end design activities for Display Sub-system that deliver cutting edge solution for various Qualcomm business unit like VR, AR, Compute, IOT, Mobile. Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check, and formal verification for IP blocks. Work closely with technology/circuit design team to close IP block specification/requirement. Work closely with verification/physical design team to complete the IP design implementation. Support SoC team to integrate Display Sub-system IP solution into various SoC chips and front-end design flows. Work closely with system/software/test team to enable the low power feature in wireless SoC product. Evaluate new low-power technologies and analyze their applications to address requirements. Understand and perform block & chip-level performance analysis & identify performance bottleneck and provide required solution. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum of 5+ years"™ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm Chennai is looking for a VLSI engineers who is passionate in to work with cross-functional engineering teams . In this position, the engineer will be involved in all stages of the design and development cycles Strong knowledge of digital design and SOC architecture. Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C Experience in HDL such as Verilog Knowledge of ARM/DSP CPU architecture, High Speed Peripherals like USB2/3, PCIE or Audio/Multimedia Familiarity with Power-aware Verification, GLS, Test vector generation is a plus Exposure to Version managers like Clearcase/perforce Scripting language like Perl, Tcl or Python Analytical and Debugging skills 2-4 yrs experience Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Bachelors / Masters degree in electrical or electronics engineering with 2 - 4 yrs of experience is preferred

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: QCT's Bangalore Wireless R&D HW team is looking out for experienced Wireless Modem HW model developers to work on Qualcomm"™s best in class chipsets in modem WWAN IPs Roles and Responsibilities You will be contributing to flagship modem core IP development covering 5G(NR) & 4G (LTE) technologies. You will be part of team defining and developing next generation multi-mode 5G modems. You will be working on development and verification of HW models of modem core IP. The models are developed on C++/SystemC platform and used as golden reference for RTL verification and pre Silicon FW development ( virtual prototyping). The candidate must be well versed with C++ and should have good exposure to SystemC and/or System Verilog and/or Matlab. The candidate must have ability to understand HW micro-architecture & its modeling abstraction. Working knowledge of physical layer of wireless technologies like NR,LTE , WLAN, Bluetooth is highly desired. Expertise on digital signal processing and working experience on HW modeling and/or RTL design/ verification of IP are preferred. Candidates with SW/FW background on wireless IP can also apply. Candidates with strong technical knowhow on non-wireless DSP based HW IPs ( with Design / Verification/ Modeling skills) will also be considered. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: We are seeking a highly skilled and experienced SoC Management IP Design lead to join our team. This position requires overseeing the development of all SoC Management IPs primarily Debug and Timer IPs, which includes creating micro-architecture specifications, IP design and verification. The ideal candidate will have a strong background in IP development and SoC Management Architecture, with a focus on both technical leadership and management responsibilities. IP Design, Verification and Delivery SoC and Platform Architecture Development Key Responsibilities Leadership and Management Lead and manage the development of SoC management IPs, Primarily Debug and Timer IPs IP Design, Verification and Delivery Provide technical leadership and guidance to the IP development team. Oversee the entire lifecycle of IP development, from concept to implementation and validation. Collaborate with cross-functional teams to ensure seamless integration of IPs into SoC designs. Technical Expertise Experience of RTL design for complex SoC development using Verilog and/or SystemVerilog Experience with Arm-based designs and/or Arm System Architectures Drive the architecture and design of SoC Management IPs. Ensure the IPs meet performance, power, and area requirements. Stay updated with the latest industry trends and technologies in SoC management and IP development. Troubleshoot and resolve complex technical issues related to IPs. Collaboration and Communication Work closely with other engineering teams, including SoC design, verification, and validation teams. Foster a collaborative and innovative work environment. Communicate effectively with team members, management, and external partners. Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in SoC Management IP development, including debug and timers IPs. Strong technical leadership and management skills. Excellent understanding of SoC architecture and design principles. Strong problem-solving and analytical skills. Excellent communication and interpersonal skills. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Summary: Position for 5-8 years of experience in design verification of complex Qualcomm propriety DSP/NPU IP DSP team is responsible for delivering high-performance DSP/NPU cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space, AI, Automotive and more. Qualcomm is one of the largest fabless semiconductor design companies in the world, generating over $35 Billion in annual revenues from chipsets and royalties from intellectual property. Job Responsibilities: Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, power, post silicon and back-end teams. Implement and improve System Verilog/UVM Testbench Architecture. Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency. Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals. Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails and bugs. Complete all required verification activities at IP level and ensure high quality commercial success of our products. Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a daily basis. Responsible gate level simulation bring-up, gate level verification with timing simulations. Responsible for power aware RTL verification and gate level simulation. Skillset/Experience: 5-8 years experience in processor/ASIC design verification Solid background and understanding of Digital Design, Processor Architecture , Processor Verification and Power aware verification. Expertise in System Verilog Testbench Architecture and implementation. Experience in writing C based and assembly level testcases is preferred. Exposure to power aware implementation and verification using UPF is a plus. Experience with advanced verification techniques such as formal and assertions is a plus. Gate-Level Simulation and Debug "” 0-delay, timing annotated and power aware. Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence . Scripting/Automation Skills "” Perl, Python, Shell, Make file TCI . Solid analytical and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts. Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog is preferred. Experience in verification of Processor subsystems is preferred. Experience in creating validation suite and building automation. Should have excellent inter-personal and communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. About The Role Join Qualcomm's design verification team in verifying the high-speed mixed-signal IP designs ( PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, Sensors, etc.) for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle, from system-level concept to tape out and post-silicon support. Responsibilities Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team. Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Analog/mixed signal simulation, Low power verification, Formal verification and Gate level simulation to ensure high design quality. Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure. Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post-silicon validation. Minimum Qualifications Master's/Bachelor"™s degree in Electrical Engineering, Computer Engineering, or related field. 8+ years ASIC design verification, or related work experience. Knowledge of a HVL methodology like SystemVerilog/UVM. Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others. Preferred Qualifications Experience with Low power design verification, Formal verification and Gate level simulation. Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc., Experience in scripting languages (Python, or Perl). Experience with mixed-signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, Data Convertors (DAC, ADC), or sensors.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 3+ years"™ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications 6-9 years of experience in SoC design Educational Requirements6+ years of experience with a Bachelor"™s/ Master"™s degree in Electrical engineering

Role & responsibilities Design and implement complex digital systems using Verilog and/or VHDL. Develop and optimize digital signal processing algorithms for implementation on FPGAs. Perform simulation and verification of RTL code using tools like ModelSim, Questa, or Vivado. Debug and troubleshoot FPGA-based systems using logic analyzers, oscilloscopes, and on-chip debugging tools (e.g., ChipScope/ILA). Work closely with hardware and software teams to ensure seamless integration of FPGA designs into larger systems. Optimize performance, power, and area (PPA) of FPGA designs. Perform synthesis, place and route, and generate bitstreams using tools such as Xilinx Vivado or Intel Quartus. Write testbenches and conduct unit and system-level testing. Document design specifications, processes, and test results.

An experienced and passionate ASIC Digital Verification Engineer with a deep understanding of RTL-based IP cores and complex protocols. You have over 12 years of experience in functional verification and are adept at making architectural decisions for test bench designs. You are proficient in SystemVerilog (SV) and Universal Verification Methodology (UVM), and you have a proven track record of implementing coverage-driven methodologies. You bring a wealth of knowledge in protocols such as DDR, PCIe, AMBA, and more. Your technical expertise is matched by your strong communication skills, ability to work independently, and your innovative problem-solving capabilities. Your experience may also include familiarity with functional safety standards such as ISO26262 and FMEDA. What You ll Be Doing: Making architectural decisions on test bench design. Writing verification plans and specifications. Implementing test bench infrastructure and writing test cases. Implementing a coverage-driven methodology. Leading technical aspects of verification projects. Collaborating with international teams of architects, designers, and verification engineers. The Impact You Will Have: Enhancing the robustness and reliability of IP cores used in critical applications. Driving innovation in verification methodologies and tools. Ensuring high-quality deliverables through rigorous verification processes. Improving productivity, performance, and throughput of verification solutions. Contributing to the success of Synopsys customers in industries such as AI, automotive, and server farms. Mentoring and guiding junior engineers in the verification domain. What You ll Need: Knowledge of protocols such as DDR, PCIe, AMBA (AXI, CHI), SD/eMMC, Ethernet, USB, MIPI. Hands-on experience with UVM/VMM/OVM, test planning, and coverage closure. Proficiency in SystemVerilog and UVM, object-oriented coding, and verification. Experience with scripting languages like C/C++, TCL, Perl, Python. Experience with functional safety standards such as ISO26262 and FMEDA (preferred). Who You Are: Independent and precise in your work. Innovative and proactive in problem-solving. Excellent communicator and team player. Detail-oriented with a strong analytical mindset. Eager to learn and grow within a technical role

Defining and developing ASIC RTL design and verification at both chip and block levels. Writing and modifying test cases, checkers, and scoreboards in a system Verilog-based test environment. Collaborating with cross-functional teams to ensure seamless integration of analog and digital components. Conducting AMS verification, particularly for high-speed SerDes designs supporting multi-protocols. Utilizing Synopsys analog mixed-signal design tools for efficient design and verification processes. Programming and scripting using TCL, Perl, and Python to automate and streamline workflows. The Impact You Will Have: Enhancing the performance and reliability of our high-performance silicon chips. Contributing to the development of innovative technologies that drive the Era of Pervasive Intelligence. Improving the efficiency and effectiveness of our design and verification processes. Ensuring the seamless integration of analog and digital components in our products. Supporting the creation of cutting-edge solutions for self-driving cars, learning machines, and more. Driving continuous technological innovation within Synopsys and the broader industry. What You ll Need: Looking for 2+yrs experience with BTech / MTech in VLSI / Electronics/ Microelectronics Knowledge or hands-on expertise/analysis of Analog and digital CMOS circuit designs Knowledge on electrical circuit networks and analysis Knowledge or hands-on Verilog/System Verilog languages and supported methodologies like VMM, UVM Must be able write/modify testcases, checkers, scoreboards in a system Verilog based test environment AMS verification experience in high speed Serdes designs supporting multi-protocols is an advantage. Experience with the Synopsys Analog mixed-signal design tool set is an advantage. Modelling languages Verilog-a/ams can be an advantage Programming/scripting know-how e. g. tcl, perl, python Experience with Linux Good communication skills, ability to take ownership Self-organized to ensure that project timescales are met Who You Are: Excellent communicator with strong interpersonal skills. Proactive and able to take ownership of projects. Self-organized and capable of managing time effectively. Collaborative team player who thrives in a dynamic environment. Detail-oriented and committed to delivering high-quality results.

You are a highly motivated and experienced professional with a deep understanding of VLSI design and a strong background in high-speed protocols such as Ethernet, DDR, and PCIe Your technical expertise is complemented by your hands-on experience in simulation, synthesis, and static timing analysis (STA) With a Bachelors and/or Masters Degree in Electrical Engineering or a related field, you bring at least 10 years of design, verification, or application engineering experience to the table You thrive in a UNIX environment and are proficient with ASIC/SoC tape-out processes from concept to full production Your ability to work across teams, coupled with strong analytical, reasoning, and problem-solving skills, sets you apart as a creative and results-oriented professional Excellent verbal and written communication skills in English are essential, as you will be collaborating with customers and teams worldwide Occasional travel is something you are comfortable with, and you are ready to take on the challenge of integrating leading Interface IP into next-generation products What You ll Be Doing: Acting as a trusted advisor for our Interface IP customers, providing guidance throughout their SoC flow. Supporting customers in resolving technical challenges and performing integration reviews at key milestones. Assisting with silicon/system bring-up and debugging critical issues. Collaborating with internal teams to deliver tailored solutions to customers. Staying updated with the latest industry specifications and applications in various hot market segments. Participating in occasional travel to support customer engagements and silicon bring-up activities. The Impact You Will Have: Enhancing the usability and adoption of Synopsys Interface IP products by providing expert technical support. Facilitating successful integration of IP into customer designs, contributing to their product development timelines. Improving customer satisfaction by resolving technical issues efficiently and effectively. Driving innovation by working with cutting-edge technologies and industry specifications. Strengthening Synopsys market position through successful customer engagements and support. Contributing to the development of next-generation products that leverage high-speed protocols and advanced IP. What You ll Need: Bachelors and/or Masters Degree in Electrical Engineering or similar with a focus on VLSI design. At least 10 years of design, verification, or application engineering experience. Proficiency in RTL coding using Verilog/VHDL. Experience with high-speed protocols such as Ethernet, DDR, and PCIe. Hands-on experience with simulation, synthesis, and static timing analysis (STA). Familiarity with UNIX environments and ASIC/SoC tape-out processes. Knowledge of CDC, RDC, Lint, DFT, STA, and LEC is a plus. Who You Are: Creative and results-oriented, capable of managing multiple tasks concurrently. Strong verbal and written communication skills in English. Ability to work collaboratively across teams to deliver solutions to customers. Strong analytical, reasoning, and problem-solving skills. Willingness to travel occasionally to support customer engagements.

You will get an opportunity to work on latest Synopsys implementation technologies (Machine Learning, Physical Synthesis , Multi-Source CTS, etc.) to solve complex PPA challenges faced by Synopsys customers. Working on benchmarks to displace competition implementation solutions. Working on developing and debugging RTL-GDS implementation methodologies and flows. Providing technical solutions by identifying the design and/or EDA tool issues and provide an appropriate solution for customers. Effectively translate the findings into requirements for R&D to improve both tool behavior with enhancements as adaptive long-term solutions. Involved in deployment of new technologies on latest EDA versions and enable customers to migrate to newer versions achieving best PPA. Coming up with a proactive understanding of customers pain point and coming up with innovative solutions to address the same. Closely interacting with Synopsys R&D team and product development team to develop future technologies. This role requires you to act as customers advocate while talking to inhouse R&D and be a product brand ambassador while engaging with customers. The candidate must have good exposure to methodology changes to achieve targeted PPA metrics for complex designs. At least 2 years of experience in Physical Implementation RTL-GDS. Experience in autonomously debugging and resolving synth & PnR implementation challenges. Proficiency in Synopsys implementation tools is an advantage. The individual must be self-motivated and dedicated with strong debugging skills. Requires proficiency in scripting (tcl / unix / perl). Excellent communication skills including the ability to interface with customers and business unit personnel are essential.

Working with Synopsys customers to understand their needs and define verification scope and activities. Understanding the complexity and requirements of verification and proposing resource requirements to complete the activities. Leading a team of engineers to perform various pre-silicon verification activities on IPs/Subsystems. Anticipating problems and risks and working towards a resolution and risk mitigation plan. Assisting and mentoring the team in day-to-day activities and growing the capabilities of the verification team for future assignments. Reviewing various results and reports to provide continuous feedback to the team and improve the quality of deliverables. Reporting status to management and providing suggestions to resolve any issues that may impact execution. Collaborating with architects, designers, and pre and post-silicon verification teams to accomplish your tasks. Adhering to quality standards and good test and verification practices. Ramping up on new Verification tools and methodologies using Synopsys Products to enable customers. Working with other Synopsys teams including BU AEs and Sales to develop, broaden, and deploy Tool and IP solutions. The Impact You Will Have: Driving the success of customer projects by ensuring robust and thorough verification of SoC designs. Enhancing Synopsys reputation as a leader in verification through high-quality deliverables and customer satisfaction. Mentoring and growing the verification team, building a strong foundation for future projects. Identifying and mitigating risks early, ensuring smooth project execution and delivery. Improving verification methodologies and practices, contributing to the overall efficiency and effectiveness of the team. Collaborating with cross-functional teams to achieve seamless integration and execution of verification activities. Providing valuable feedback and insights that drive continuous improvement in verification processes and tools. What You ll Need: B.E/B. Tech/M.E/M. Tech in electronics with a minimum of 12+ years experience in SoC/IP/Subsystems verification domain. Technical expertise in various aspects of pre-silicon Verification (UVM, Coverage Analysis, Verification plan creation, debugging, etc). Good knowledge of various protocols (PCIe, Ethernet, USB, DDR, etc) and/or processor/interconnect/debug architecture. Hands-on experience with verification tools such as VCS, waveform analyzers, and third-party VIP integration (such as Synopsys VIPs). Ability to lead a team to perform verification on complex SoC/IP/Subsystems. Experience with planning and managing verification activities for SoC/Subsystems/IPs. Strong understanding of design concepts, ASIC flows, and stakeholders. Good communication skills. Who You Are: A proactive and detail-oriented leader who can guide and mentor a team. An excellent communicator who can collaborate effectively with cross-functional teams. A problem-solver who can anticipate challenges and develop effective mitigation strategies. A continuous learner who stays updated with the latest verification tools and methodologies. A team player who values quality and strives for excellence in deliverables