806 Rtl Jobs - Page 10

About QpiAI: QpiAI is at the forefront of discovering optimal AI and Quantum systems across various industries including Life sciences, Healthcare, Transportation, Finance, Industrial, and Space technologies. Specializing in building full stack Enterprise Quantum Computers, the Quantum hardware team at QpiAI is dedicated to the design and characterization of Quantum Processor, Cryogenic Quantum Control Circuits, RF Control Hardware, and QpiAI ASGP. We are looking for a talented Hardware Design Engineer to join our innovative team. Together, we aim to develop cutting-edge custom hardware for Quantum computers that have the potential to revolutionize various sectors. If you are a self-driven individual with a solid grasp of building complex SOC and IPs, possess a deep understanding of client requirements, and are familiar with different development cycles, then this opportunity is tailored for you. Responsibilities: - Engage in micro-architecture development and document specifications. - Implement designs in RTL and collaborate with the verification team to ensure functionality. - Utilize logic design expertise to optimize performance and power objectives. - Produce a synthesis/timing clean design while cooperating with the physical design team for a routable and physically implementable design. Requirements: - Bachelor's degree in electrical engineering or computer engineering. - 3+ years of experience in chip design development for complex designs. - Proficiency in logic design, Verilog, and/or System-Verilog, with a strong understanding of physical design and VLSI. - Excellent interpersonal skills and a team player mindset. - Familiarity with design reuse, including RTL, constraints, and waiver. - Experience in handling timing constraints and exceptions. - Ability to conduct standard quality checks such as LINT and CDC. Join us at QpiAI and be part of a dynamic team driving advancements in Quantum computing hardware to shape the future of technology across multiple industries.,

Eximietas is currently seeking Senior Physical Design Leads/Managers with over 10 years of experience for a position in Visakhapatnam. Qualifications: - Minimum of 10+ years of experience in Physical Design using mainstream P&R tools - Bachelors or Masters Degree in Electronics, Electrical, Telecom, or VLSI Engineering Responsibilities: - Work on designs using 10nm/7nm/5nm or lower nodes with various customers to meet performance, area, and power targets - Develop flow and methodology for placement, CTS, and routing - Provide training and technical support to customers Required Expertise: - Strong background in place & route flow, including placement guidelines, clock-tree synthesis, routing, and timing optimizations - Experience in hierarchical designs and/or Low Power implementation is a plus - Familiarity with Synthesis, floor plan design, Static Timing Analysis, and Physical Verification (DRC/LVS/DFM) Interested candidates are encouraged to send their resumes to maruthiprasad.e@eximietas.design.,

Build your career with Sykatiya Technologies, a company that values Technical Ability and the Attitude of its highly talented team. Our team consists of skilled engineers and experts from various domains such as Design Verification, DFT/Test, Physical Design, and Analog Design for ASICs. We are currently looking for candidates for the role of RTL/ IP Design with 3-12 years of experience to join our team in Bangalore. As an ideal candidate, you should have at least 5 years of experience in digital ASIC front-end design. You should possess a thorough understanding of design flows including RTL (VHDL, Verilog, and/or SystemVerilog). Experience with simulation tools like Questa or Xcelium and logic synthesis tools such as Synopsys DC is highly desirable. Candidates applying for this position should also have experience working with embedded microcontrollers and AMBA bus systems. A Bachelor's degree in science or engineering and proficiency in English communication are essential requirements for this role. If you are passionate about ASIC design and meet the above qualifications, we encourage you to apply and be a part of our dynamic team at Sykatiya Technologies.,

Qualcomm India Private Limited is looking for a skilled individual to join their Engineering Group, specifically focusing on Hardware Engineering. As a member of Qualcomm, you will be part of a team of inventors who have paved the way for 5G technology, leading to a new era of connectivity and endless possibilities that will revolutionize industries, generate employment opportunities, and improve lives. This is just the beginning of the Invention Age, and your expertise is crucial in turning 5G's potential into groundbreaking technologies and products. At Qualcomm CDMA Technologies (QCT), a prominent player in Multimedia integrated circuits, software, and systems for wireless consumer devices, including Smartphones, Netbooks, and E-readers, you will be involved in developing cutting-edge technologies to enhance mobile devices across various domains such as 2D and 3D graphics, audio/video, display, and architecture. Your role will encompass the design and implementation of leading-edge graphics processors, focusing on areas like 2D and 3D graphics, streaming processors, high-speed IO interfaces, and bus protocols. You will be responsible for the architecture and micro-architecture design of the ASIC, RTL design and synthesis, as well as logic and timing verification. The successful candidate will work on specifying and designing digital blocks in the Multimedia Graphics team to be integrated into a wide range of devices. Collaboration and active support for diversity within the team and the company are expected from all Qualcomm employees. **Minimum Qualifications:** - Bachelor's degree in Science, Engineering, or a related field - Previous experience in designing GPU or CPU cores and ASICs for Multimedia and Graphics applications in deep sub-micron CMOS processes for volume production - Experience with Verilog/VHDL design, Synopsys synthesis, static timing analysis, formal verification, low power design, test plan development, coverage-based design verification, and design-for-test (DFT) - Knowledge of Computer Architecture, Computer Arithmetic, C/C++ programming languages is desired - Exposure to DX9~12 level graphics HW development is an advantage - Strong communication skills and a collaborative mindset - Required: Bachelor's degree in Computer Science, Electrical Engineering, Information Systems, or related field. - Preferred: Master's degree in Computer Science, Electrical Engineering, Information Systems, or related field. **Additional Requirements:** - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with 6+ years of Hardware Engineering or related work experience - OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with 5+ years of Hardware Engineering or related work experience - OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with 4+ years of Hardware Engineering or related work experience Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. Reasonable accommodations will be provided upon request to support individuals with disabilities throughout the hiring process. Employees are expected to adhere to all applicable policies and procedures, including those related to confidentiality and security protocols. Please note that Qualcomm does not accept unsolicited resumes or applications from agencies. This job posting is intended for individuals seeking direct employment with Qualcomm. For more information about this role, please reach out to Qualcomm Careers directly.,

Job Summary 8-12 years of experience in SoC/IP Design. Expertise in Writing Detailed IP Specifications, Micro Architecture, IP design, Subsystem and SoC level integration. Expertise on RTL Development. Follow Coding Standards, expertise on Lint, CDC tools, Verification and Debugging of test cases, code and functional coverage analysis. In-depth knowledge of Clocking Methodology, Low Power Implementation. Hands on experience on writing constraints and exceptions, performing Synthesis, Timing Analysis and Design for Test Implementation. Experience of power partitioning and usage of CPF/UPF. Exposure to IP Design for ARM Microcontrollers based SoCs. Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB). Knowledge of one or more of the interface protocols, PCIe, DDR, Ethernet, I2C, UART, SPI. Experience in Matlab Simulations and Implementing Signal Processing IPs like Digital Filters, Math Functions or FFT engines. Experience in developing Security IPs for various Encryption standards. Experience in implementing On-chip Memory and Flash controllers.

As a React Developer at our company, you will be responsible for building modern, scalable UIs and integrating AI-powered features into our product. You will collaborate closely with design, product, and backend teams to deliver high-impact user experiences. Your main responsibilities will include: - Building advanced UIs using React, Hooks, and TypeScript - Managing state with Redux Toolkit, Zustand, or similar tools - Working with REST & GraphQL APIs - Integrating AI features using OpenAI APIs such as ChatGPT and DALLE - Utilizing modern styling tools like Tailwind CSS or Styled Components - Writing clean and testable code with tools like Jest and RTL - Collaborating effectively within Agile teams To excel in this role, you should have the following skills: - Strong proficiency in JavaScript (ES6+) and TypeScript - Experience with AI API integration, specifically with platforms like OpenAI and LangChain - Familiarity with build tools such as Vite/Webpack, CI/CD practices, and Git - Good UX/product thinking abilities and effective communication skills - Bonus points for experience with Next.js, knowledge of vector search, and familiarity with chatbots or streaming AI UIs We are looking for candidates with a minimum of 4 years of relevant experience. This is a full-time position based in Kochi. If you are interested in this opportunity, please send your resume to careers@cabotsolutions.com.,

As a Senior React Engineer, you will be expected to demonstrate a high level of proficiency in React, Redux, HTML, CSS, JavaScript, Jest, and RTL for unit test automation. Your primary responsibilities will include utilizing your strong expertise in React and Redux to develop dynamic web applications. You should possess a deep understanding of HTML, CSS, and JavaScript (ES6+), as well as hands-on experience with unit testing frameworks, particularly Jest and React Testing Library (RTL). Familiarity with design-to-code solutions and tools like Builder.io will be an added advantage. In addition, you are required to have a solid grasp of responsive design principles and cross-browser compatibility. Your problem-solving abilities and meticulous attention to detail will be crucial in ensuring the quality and functionality of the applications you develop. Furthermore, effective communication and collaboration skills are essential for seamless teamwork with fellow UI engineers, Product teams, and other Engineers. Your ability to work cohesively with cross-functional teams will play a key role in delivering successful projects and achieving collective goals.,

As a Senior Silicon Design Engineer at AMD, you will play a key role in contributing to the development and verification of cutting-edge technologies that drive innovation in the computing industry. Your passion for modern processor architecture, digital design, and verification will be instrumental in ensuring the highest quality products are delivered to the market. In this role, you will collaborate with a diverse team of engineers to implement front-end designs from RTL to netlist, conduct formal verification checks, and debug any timing, area, or congestion issues that may arise. Your ability to analyze inter-block timing and develop timing constraints will be crucial in optimizing the performance of the designs. Key responsibilities include running logic/physical synthesis, performing power estimation, and developing automation scripts for various front-end tools. Your strong analytical and problem-solving skills will be essential in identifying and addressing potential design issues, as well as working closely with architects, RTL designers, and SOC teams to ensure efficient IP quality. To excel in this role, you should have 5 to 10 years of experience in front-end implementation, familiarity with power analysis, and a background in computing/graphics. A Bachelor's or Master's degree in computer engineering or electrical engineering is required to be successful in this position. Join us at AMD and be part of a team that is dedicated to pushing the limits of innovation and solving the world's most important challenges. Together, we advance towards a future where technology enriches lives and transforms industries.,

You are invited to join Evon Technologies Pvt. Ltd., a team of over 450 technologists dedicated to providing software services and consultation to international clients. As a CMMI Level 3 company and recognized as the Top Mobile App Development Co. of 2021, we are currently engaged in various projects involving iOS, Android, Java, HTML, PHP, Ruby on Rails, Phone Gap, .Net, Angular, Node, React, Salesforce, PowerBI, and other cutting-edge technologies. Our company is expanding rapidly, and we are seeking individuals who are intelligent, dedicated, and poised to enhance our existing teams. We are currently seeking FPGA/RTL Developers who possess the following qualities: intelligence, pragmatism, self-motivation, and a willingness to learn and contribute to both organizational and personal advancement. This position is based in Dehradun and requires candidates who are available immediately. Qualifications for this role include a minimum of 3 years of experience in software development using FPGA, expertise in physical layer signal processing, proficiency in Verilog/VHDL, and hands-on experience with Xilinx FPGA (vivado). Additionally, candidates should have experience in DO-254 based development and documentation. The ideal candidate will have a background in Design Engineering, Electrical Engineering, or Product Design, possess skills in Computer-Aided Design (CAD), demonstrate strong analytical and problem-solving abilities, be knowledgeable in FPGA and RTL design methodologies, and hold a Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. If you meet these qualifications and are interested in this opportunity, please email your resume to ethi.sharma@evontech.com.,

You should have 3+ years of experience in RTL, UPF & Physical aware Synthesis for cutting-edge technology nodes, logic equivalence checking, Scripting, and Netlist Timing Signoff. Proficiency in Python/Tcl is required. You should be familiar with Synthesis tools such as Fusion Compiler/Genus and have fair knowledge in LEC, LP signoff tools. Proficiency in VLSI front-end design steps including Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking is essential. Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus. You should be sincere, dedicated, and willing to take up new challenges. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Qualcomm is an equal opportunity employer that provides reasonable accommodations for individuals with disabilities during the application/hiring process. If you require accommodations, you may contact Qualcomm at disability-accommodations@qualcomm.com. Qualcomm expects its employees to adhere to all applicable policies and procedures, including security and confidentiality requirements regarding Company confidential information and other proprietary data. Please note that Qualcomm's Careers Site is for individuals seeking jobs at Qualcomm. Staffing and recruiting agencies are not authorized to use this site for submissions. Qualcomm does not accept unsolicited resumes or applications from agencies. For more information about this role, kindly contact Qualcomm Careers. 3074295,

Job description About The Role Come join Intel's highly regarded Devices Development Group, responsible for creating Client SOCs. We envision the future of computing and design for the next generation of laptop and desktop computers. We are looking for a SoC Physical Design Engineer, who is ready to research, design, develop, and test lead Intel designs as we reimagine how to build SoCs at Intel and in the semiconductor industry. Our bold purpose as a company is to create world-changing technology that enriches the lives of every person on earth and this role is instrumental in furthering our mission to shape the future of technology. Your responsibilities may include but not be limited to: Performing physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Physical Synthesis, Floor planning, Place and Route, Clock Tree Synthesis with Synopsys and/or Cadence EDA tools. Multiple Power Domain analysis and handling using standard Power Formats UPF or CPF. Verification and Signoff including Formal Equivalence Verification, Static Timing Analysis, Reliability Verification, Static and Dynamic power integrity, Layout Verification, Electrical rule checking, Noise analysis and Structural Design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Participating in the development and improvement of physical design methodologies and flow automation. Driving performance optimization, including co-optimization, work with process teams, to create best-in-class designs. The ideal candidate should exhibit behavioral traits that indicate: Self-motivator with strong problem-solving skills. Excellent interpersonal skills, including written, verbal, and presentation communications. Attention to detail and organizational skills. Ability to work as part of a team and collaborate in a high-paced atmosphere. Qualifications BS/BTech degree with 8 years of experience, or MS/MTech degree with 6 years of experience, in Electronics Computer Engineering, or a related field.

Job description About The Role Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the AI SOC / CPU IP block for integration in full chip designs. Participates actively in the definition of architecture and microarchitecture features of the AI SOC/CPU being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Documents micro architectural specs (MAS) of the CPU features being designed. Supports SoC customers to ensure high quality integration of the CPU block. Qualifications Minimum Qualifications: Bachelor's with 13+ Years and Master's with 10+ Years of relevant experience in the semiconductor industry. 10+ years of experience in/withVerilog and system Verilog, synthesizable RTL Modern design techniques and energy-efficient/low power logic design and power analysis. 5+ years of experience in/withHaving achieved multiple tape-outs reaching production with first pass silicon. Hands on experience with FPGA emulation, silicon bring-up, characterization and debug.

Job description About The Role Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure highquality integration and verification of the IP block. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications Minimum QualificationsGraduate of Bachelor's Degree in Electrical Engineering, Computer Engineering, or a related field with at least 6+ years experience in the following:Micro-architecture and RTL design for advanced SoCsExpertise in link and network layers of coherent fabric systemsHands-on experience in developing protocol bridges for interface translations; and experience with coherent protocols (CXL, CCIX, PCIe, or similar) and interconnect technologies OR;Graduate of Master's Degree in Electrical Engineering, Computer Engineering, or a related field with at least 4+ years experience in the followingMicro-architecture and RTL design for advanced SoCsExpertise in link and network layers of coherent fabric systemsHands-on experience in developing protocol bridges for interface translations; and experience with coherent protocols (CXL, CCIX, PCIe, or similar) and interconnect technologies OR;PhD in Electrical Engineering, Computer Engineering, or a related field.Technical Experience- Proficiency in RTL design using Verilog or SystemVerilog.- Knowledge in micro-architecture and pipeline design.- Expertise in simulation, debugging, and performance tuning tools.- Knowledge in scripting languages (Python, Perl, or TCL) for automation and design flow optimization.

Job description Seize the opportunity to work with the team responsible for RTL logic design and microarchitecture of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team, CLIPS is responsible for developing soft IPs, subsystems and gaskets for client and server chipsets.Candidate will be responsible for logic design and development, responsibilities including but not limited to: Develops the logic design, register transfer level (RTL) coding, and simulation for an IP design. Participates in the definition of microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for meet the design specification requirements. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Supports SOC to integrate and validate the IP on need basis. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Qualifications : BE/ME/Btech/ Mtech in computer science eng or electronics and Communications. The candidate must possess a minimum of Bachelor Degree in Electronics Engineering, Computer Engineering, Computer Science or equivalent. The candidate should have successful track record of hardware development experience and demonstrated technical leadership skills. The candidate must have demonstrated the ability to solve highly complex technical problems with excellent communication skills. The candidate must also have demonstrated strong ethical standards. Must also be able to perform in a highly ambiguous and dynamic business environment. Skills : Relevant experience with skills in ASIC IP design flows, RTL coding and Globals (Clocking, Boot/ Reset/Fabrics, DfD, Fuse, etc) with experience in CDC, linting, spyglass, micro-architecture. Experience in subsystem design and IO protocols such as AMBA, USB, PCIe, UCIe, UFS, SATA, UART, SPI, I2C, I3C etc is a plus. Other technical requirements: 3 to 8 years of relevant pre-silicon logic design experience in ASIC domain. Experienced with various tools and methodologies including but not limited to: System Verilog, Python/Perl/ Shell scripting, Synopsys tools, RTL model build, design-for-test, design-for-verification. Experienced in EDA tools & flows such as Spyglass VCLINT, VCLP, VC-CDC, SG-DFT, Design Complier, Calibre, Fishtail, FEV, ATPG etc. Experienced in developing micro-architecture based on High Level Architecture specifications. Experienced in VLSI or Structural and Physical design flow and methodology. Experienced in Power-aware design and reviewing validation flows. Strong Chipset or CPU level understanding required on power consumption, power estimation and low power design methods.

As an experienced React.js Developer, you will play a crucial role in building scalable and maintainable frontends in enterprise-level environments. Your expertise in micro-frontend architectures and frontend system design will be key as you work on large-scale web applications that impact user experience and architectural stability. Your responsibilities will include architecting and implementing modern React.js applications using the latest features such as Hooks and Context. You will also develop and maintain micro-frontend modules that seamlessly integrate with large-scale platforms. Additionally, you will lead and participate in frontend system design discussions, code reviews, and technical planning sessions. Collaboration with product, design, and backend teams is essential to ensure the timely delivery of high-quality features. You will be tasked with optimizing application performance, memory usage, and loading time while adhering to best practices around component architecture, state management, and code modularity. Furthermore, you will be responsible for setting up and maintaining scalable and maintainable frontend codebases following enterprise standards. Your code should be clean, reusable, and well-documented, with appropriate testing using tools like Jest and RTL. Mentoring junior developers and supporting continuous frontend knowledge sharing will also be part of your role. If you are passionate about clean, well-tested code and have a strong background in React.js development, we encourage you to apply and be a part of our fast-moving, product-driven team dedicated to delivering exceptional user experiences.,

The ideal candidate for this position should have 1-2 years of experience in AMS design verification. You will be responsible for developing Verilog/VerilogA/VerilogAMS models for signal and power management modules to support top-level verification. Experience in full chip DV would be an added advantage. You will contribute to the development of the Full-Chip AMS-DV plan and own significant pieces of this verification process. It is essential to have the ability to drive best practices in the field of AMS-DV. In this role, you will work independently to identify bugs and resolve them formally with cross-functional teams. An understanding of analog power IPs will be beneficial as it can help in the debugging of chip-level AMS bugs. Proficiency in using tools such as Cadence Virtuoso, Spectre & Spice simulation, Incisive, and AMS simulators is required. You will utilize RTL and Gates+SDF, including process variation in back-annotated timing simulations. This will involve verifying chip-level timing between analog and digital circuits, parasitic resistance and capacitance, and using Assura parasitic extraction tools. Experience in constrained-random stimulus and auto-checking verification environments, especially constrained-random analog stimulus, is desired. The successful candidate should be able to work efficiently in a fast-paced product development environment. You will manage bug tracking and RTL code coverage, collaborate with design and systems teams to address bugs as they arise, and review digital and analog designs to provide guidance on Design for Verification architecture and features during chip development.,

YASH Technologies is a leading technology integrator specializing in helping clients reimagine operating models, enhance competitiveness, optimize costs, foster exceptional stakeholder experiences, and drive business transformation. At YASH, you will be part of a team of talented individuals working with cutting-edge technologies. Our purpose is anchored in bringing real positive changes in an increasingly virtual world, transcending generational gaps and future disruptions. We are currently seeking React JS Professionals in the following areas: Roles And Responsibilities: - Collaborate in a team or work independently to design, develop, and test web-based applications. - Design, develop, test, and document high-quality software based on user and functional requirements within specified timelines and in adherence to coding standards. - Develop rapid prototypes for feasibility testing and prepare all relevant documentation for software operation. - Follow established development systems, processes, and procedures to ensure efficient, effective, and high-quality project delivery. - Maintain effective communication with all stakeholders and execute tasks as directed by the Delivery Lead/Team Lead. Qualifications And/or Experience: - Minimum 5 years of experience as a UI Developer with a strong focus on UI design. - Proficiency in developing User Interfaces using various Front-end technologies such as SSR, SPA, and PWA Apps. - Strong hands-on experience in React, Redux, Typescript, JavaScript, HTML5, CSS3, and related technologies for code analysis and development. - Sound knowledge of cross-browser compatibility, cross-platform development, Server-side rendering, and Micro Frontends. - Experience in RESTful API integration, application performance analysis, and tuning. - Familiarity with unit testing using Jest and RTL, along with expertise in UI Libraries like MUI, ANTD, PrimeReact, or similar. - Understanding of web accessibility concepts, CI/CD environments, Git, or similar version control tools. - Demonstrated proficiency in user interface monitoring tools. Mandatory Skills: - HTML5, CSS, JavaScript, Typescript - React, Redux, React Router, Axios - Testing Tools: Jest, RTL - Cloud Platforms: Azure/AWS Highly Desirable Skills: - Next JS - Micro Frontend - PWA At YASH, you will have the opportunity to shape a career path that aligns with your aspirations within a collaborative team environment. We embrace career-oriented skilling models and leverage technology for continuous learning, unlearning, and relearning at scale. Our Hyperlearning workplace is built on the following principles: - Flexible work arrangements, emotional positivity, and a free-spirited environment. - Agile self-determination, trust, transparency, and open collaboration. - Comprehensive support to achieve business goals. - Stable employment with a positive atmosphere and ethical corporate culture.,

The ideal candidate for this role will be an RTL engineer with over 8 years of practical design and verification experience using SystemVerilog UVM and ASIC verification. You should have hands-on experience with Synopsys and/or Cadence simulation tools, as well as proficiency in RTL and possibly Gate level debug. Desirable skills for this position include experience with Synopsys and/or Cadence Synthesis, STA, DFT, Formal Equivalence tools, and familiarity with JIRA. It would be beneficial to have knowledge of scripting languages such as Python or equivalent, understanding of PLLs, and experience with mixed-signal design modelling and debugging. Keywords: UVM, RTL, SystemVerilog, Synthesis, Analog.,

As a front-end developer at Pega, you will be an integral part of the team responsible for building cutting-edge solutions for some of the world's largest organizations. Your primary focus will be on developing the user interface for our suite of CRM applications, ensuring that it is professional, responsive, and aligned with our design system. You will collaborate closely with our design team to bring our design system to life and build the UI component library using the latest technologies and frameworks. In this role, you will have the opportunity to work on the Pega Infinity & Launchpad platform, driving the development of no-code capabilities that enable our clients to rapidly deploy amazing user interfaces. You will extend our UI library, implement UI for various applications, and collaborate with the UX design group to implement the design system into functional components. Additionally, you will focus on building accessible components and closing accessibility gaps within our applications. To excel in this role, you should have a minimum of 2-4 years of experience as a front-end developer, with expertise in ReactJS and a strong understanding of JavaScript, HTML5, CSS3, and ES6. Experience with automation scripts, CSS pre-processors, state management libraries, and front-end development tools is essential. You should also have a proven track record of developing responsive UI components that deliver an exceptional user experience. At Pega, you will have the opportunity to work in a fast-paced, collaborative, and cross-functional environment that values excellence, teamwork, and innovation. You will be part of a culture that encourages continuous learning and development, offering you the chance to interact with senior management and contribute to critical opportunities. If you are passionate about web technologies, have a keen eye for detail, and are dedicated to delivering high-quality code, then this role is perfect for you. Join us at Pega and be part of a team that is redefining how software is built and deployed. Job ID: 21721,

Job Overview We are seeking highly skilled and motivated System-on-Chip (SoC) Emulation engineers to join our diverse team at Arm! Our team focuses on performance architecture and PnP analysis of Arm SoCs/SoPs (System-on-Package), System level infrastructure (SoC/SoP/Rackscale/Podscale) in preand postsilicon environments Working closely with implementation teams and customers, we develop best-in-class silicon platforms across markets such as servers, accelerators, client, infrastructure, IoT, and automotive, Responsibilities As a member/lead of SOC emulation team you will be involved in Supporting multiple Emulation environments using the latest emulation techniques, Building early SoC platforms to facilitate performance/power analysis and debug Able to handle/modify RTL and stitch together SoCs with standardized interfaces from scratch for bare-metal and validation OS based bringups Collaboration with design teams to ensure the production of clean RTL code, Developing system level testbenches to implement performance and power benchmarks, simpoints and use cases in emulation platform Integrate observation options to assemble and debug performance/power studies, correlate with pre-Si simulation/post-Si, lead larger implementation teams for emulation at later implementation phases and work with post-Si teams for analysis/tuning Help drive innovation in model building and debugging methodologies, Collaborate with SoC Architecture team to create testplans covering all metrics for the product Define flexible/reduced SoC configurations allowing reduction in simulation and emulation capacities, while providing accurate performance estimates Collaborate with emulation vendors to define distributed systems to split huge SOC netlist between multiple emulation boxes, Required Skills and Experience Experience (8-12 years) in SoC Performance verification and emulation environment bringup in the semiconductor industry, A background in Electrical Engineering, Computer Engineering, or Computer Science with an expertise in computer architecture and microarchitecture, Proficient in RTL (SystemVerilog, Verilog, VHDL), C/C++ for bare metal code, system validation using OS, test code development, strong scripting capabilities, particularly in Python, TCL, and shell scripting, Excellent communication, and interpersonal skills with ability to convey complicated solutions, Drive early and detailed performance/power analysis as an expert Emulation Architect at Arm, focusing on diverse silicon platforms Preferred experience Experience in developing, building, and releasing large multi-billion gate hardware emulation models In-depth knowledge of key hardware emulation vendor solutions for emulation and prototyping, Experience working with design and software teams on design verification tests, PPA workloads, and software workloads, In Return We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to surpass ordinary and shape outstanding! Accommodations at Arm At Arm, we want to build extraordinary teams If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility Please email us about anything we can do to accommodate you during the recruitment process, Hybrid Working at Arm Arms approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the teams needs Details of what this means for each role will be shared upon application In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution Please talk to us to find out more about what this could look like for you, Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues We are a diverse organization of dedicated and innovative individuals, and dont discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran, Show

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience, 10 years of experience with Camera ISP image processing or other multimedia IPs such as Display or Video Codec, 10 years of experience with System Verilog Assertions (SVA), assertion-based verification, and formal verification, 4 years of experience in people management, developing employees, Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, Experience in low-power design verification, Experience working with RTL design and integration teams on methodologies that improve team productivity and velocity, Experience working with software teams to define hardware/software interfacing including control/status registers, security, and error handling, About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products You'll contribute to the innovation behind products loved by millions worldwide Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration, Google's mission is to organize the world's information and make it universally accessible and useful Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful We aim to make people's lives better through technology, Responsibilities Lead a team of individuals; set and communicate individual and team priorities that support organizational goals Meet regularly with individuals to discuss performance and development, and provide feedback and coaching, Work cross-functionally to debug failures and verify the functional correctness of the design, Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use, Plan the verification of complex Camera ISP hardware IPs at subsystem and full chip level by fully understanding the design specification and interacting with architecture and design engineers to identify important verification scenarios, Create and enhance constrained-random verification environments using System Verilog and UVM, Google is proud to be an equal opportunity workplace and is an affirmative action employer We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status We also consider qualified applicants regardless of criminal histories, consistent with legal requirements See also Google's EEO Policy and EEO is the Law If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form , Show

This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; - Grade Specific Focus on Electrical, Electronics and Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers.

Job Title: Lead RTL Design Engineer Microarchitecture (10+ Years) Company: ACL Digital Experience: 10 to 15 Years Location: [Insert Location or Remote/Hybrid] Job Type: Full Time Contact Email: prabhu.p@acldigital.com Contact Number: +91-8754387484 Job Description: ACL Digital is hiring a Lead RTL Design Engineer with strong expertise in microarchitecture and RTL design . This is a leadership role ideal for professionals with 10+ years of experience in digital design, ASIC/SoC development, and hands-on RTL coding. Key Responsibilities: Own microarchitecture and RTL development of complex IPs or subsystems. Lead block-level design from spec to synthesis and signoff. Drive RTL design using Verilog/SystemVerilog , ensuring quality and PPA targets. Guide and mentor junior RTL engineers across project cycles. Collaborate with architecture, verification, physical design, and firmware teams. Support STA, CDC, lint, synthesis, and design reviews. Contribute to methodology improvements and automation. Required Skills: 10+ years of hands-on experience in RTL design and microarchitecture . Expertise in Verilog/SystemVerilog and digital logic design. Strong knowledge of AXI, AHB , and other AMBA protocols. Experience in low-power design , clock gating, UPF, and STA. Worked on at least 1–2 successful tape-outs in a lead role. Excellent debugging, review, and technical communication skills. Good to Have: Experience with RISC-V, AI/ML accelerators, GPUs, or DSPs . Scripting knowledge: Python, Perl, or TCL. Familiarity with formal verification and FPGA prototyping . Education: B.E./B.Tech or M.E./M.Tech in ECE, Electrical, or Computer Engineering. (Ph.D. is a plus) Why Join Us? Work on cutting-edge technologies at advanced nodes (7nm/5nm/3nm). Lead high-impact projects with global teams. Grow into senior technical or architectural roles. Apply Now: Email: prabhu.p@acldigital.com Phone: +91-8754387484

SILICON DESIGN ENGINEER 2 THE ROLE: As a Silicon Design Engineer, you will work with formal experts and designers to verify formal properties and drive convergence . THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem - solving skills and are willing to learn and ready to take on problems . KEY RESPONSIBILITIES: Drive formal verification for the block and write formal properties and assertions to verify the design Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design Write tests, sequences, and testbench components in SystemVerilog and UVM along with formal to achieve verification of the design Responsible for verification quality metrics like pass rates, code coverage and functional coverage PREFERRED EXPERIENCE: Project level experience with design concepts and RTL implementation for same Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics Good understanding of computer organization/architecture ACADEMIC CREDENTIALS: Bachelor s or M aster s degree in computer engineering/Electrical Engineering #LI-SG

Description The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and re-imagined user experience through Echo and Alexa We want you to help us build on the success of our first generation of ML accelerator at edge, Work hard Have fun Make history, We are seeking a seasoned and strategic Sr DFT Engineer to Lead end-to-end Design-for-Test (DFT) planning, execution, and silicon readiness for complex SoCs This role demands deep technical expertise, hands-on ownership, and proven leadership in taking chips from design to volume production, As a Senior DFT Engineer, you will be both the technical owner and hands-on driver of the DFT strategy and execution across complex, high-performance SoCs This role requires deep technical expertise, the ability to architect scalable and robust DFT solutions, and the discipline to personally engage in implementation and debug You will work alongside world-class design, validation, and test teams to ensure first-pass silicon success and scalable production test readiness Ideal for a seasoned leader, this role combines strategic ownership with direct execution, driving full lifecycle accountability from early DFT architecture planning to high-volume silicon bring-up and yield ramp, Lead development & implementation of DFT architecture including system level DFT for a full chip Write and guide others in writing design flow and project documentation, Own DFT planning, milestone tracking, and cross-functional checklist reviews, Oversee design, insertion, and verification of DFT logic and components into full SoC and subsystem RTL netlists, Review and sign-off SoC level DFT mode timing closure using static timing analysis Drive the sign-off on a generation of high-quality test and debug patterns for high coverage on silicon Keep informed on and introduce new technology into Design-for-Test process as appropriate, Education BASIC QUALIFICATIONS BS/BE or MS/ME in Electrical Engineering, Computer Engineering, or related field, Experience 15+ years in SoC/ASIC DFT, including 3+ years Leading DFT, Proven DFT experience leading multiple SoCs/ASICs (end-to-end) from architecture to high-volume production, DFT Architecture Expertise Proven capability in architecting and implementing DFT strategies at both subsystem and top-level, including: Scan architecture, compression, and ATPG implementation for high fault coverage and test quality, MBIST, BISR, and BIHR flows, including advanced shared-bus memory BIST integration, IEEE 1149 x (Boundary Scan), IEEE 1500, and IEEE 1687 (IJTAG) test architectures, DFT-Aware STA closure, including constraint generation and timing convergence strategies for shift and capture paths, RTL and gate-level debug, including mismatch triage and simulation correlation, Insertion and Validation of EFUSE & OTP controllers and related structures during DFT implementation, Tool Proficiency Deep hands-on experience with Tessent / Industry Std EDA tools, including: IJTAG ICL extraction and PDL modeling, DFT logic insertion, pattern generation, and diagnostics, Design Background Experience in writing verilog/system verilog RTL related to DFT logic design, ATE Test Readiness Lead DFT-to-ATE handoff, including: Drive generation and sign-off of high-quality test and debug patterns to meet DFT coverage targets, Pattern validation, format conversion, and debugging across wafer sort and final test, Collaboration with PE/Test teams for silicon correlation and production test optimization, yield improvements, Silicon Debug Drive post-silicon validation, failure triage, and yield learning using SCAN diagnosis and MBIST repair signature analysis, Automation Skills Ability to build and maintain scalable DFT automation flows using Python, Tcl, or Perl, Collaboration Proven success driving cross-functional teams involving RTL, physical design, validation, PE, and manufacturing, Execution Excellence Known for being proactive, detail-oriented, and independently accountable for tapeout and post-silicon success, Leadership PREFERRED QUALIFICATIONS Led multi-site/global DFT teams, mentoring engineers and managing design reviews, Drove design-for-test planning in collaboration with customers or design services partners, Technical Depth Strong understanding of DFT-Aware yield improvement and FA, including DPPM reduction strategies, Ability to correlate pre-silicon vs ATE pattern behavior and debug marginality/escape issues, Exposure to Design-for-Debug (DfD) features like trace buffers, signature capture, and observability enhancement, Our inclusive culture empowers Amazonians to deliver the best results for our customers If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, amazon jobs / content / en / how-we-hire / accommodations for more information If the country/region youre applying in isnt listed, please contact your Recruiting Partner, Company ADCI BLR 14 SEZ Job ID: A3037331 Show