928 Rtl Design Jobs - Page 31

Greetings from Wafer Space! Exciting Opportunity for Senior RTL Design Lead Engineers Automotive SoC Domain Job Title: Senior RTL Design Engineer No. of Positions: 4 Notice Period: Immediate to 30 Days Only Referrals: Please refer only suitable and relevant profiles About the Role: We are looking for experienced RTL Design Engineers to join our team developing next-generation solutions for automotive camera and display systems. This is a key position requiring strong technical expertise in microarchitecture and RTL coding, with an emphasis on high-performance, low-power ASIC designs. Key Responsibilities: Define microarchitecture and implement RTL to meet performance, power, and area (PPA) g...

Develop verification environments for our ICs using Universal Verification Methodology (UVM); Job Description In your new role you will: create and define verification plans; develop verification environments for our ICs using Universal Verification Methodology (UVM); draw on test scenarios using SystemVerilog; verify functionality using the Constrained Random approach; develop assertions in SystemVerilog for formal verification; Interact with other disciplines, such as Concept and ApplicationEngineering, to define verification plans and strategies; provide proactive support to users of our verification flowenvironment; be responsible for our verification methods; Your Profile You are best e...

. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. . 3-10 years of experience in RTL design and Design Verification implementation for VLSI systems.

Defining and developing ASIC RTL verification at both chip and block levels. Creating and executing verification plans for complex digital designs, particularly focusing on PCIe/CXL protocols. Collaborating with cross-functional teams to ensure seamless integration and functionality of designs. Utilizing advanced verification methodologies and tools to achieve high-quality results. Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement. Communicating with internal and external stakeholders to align on project goals and deliverables. The Impact You Will Have: Enhancing the reliability and performance of Synopsys digital verification...

You have a keen eye for detail and can identify design/architecture pitfalls across clock/reset domain crossings . Your ability to synthesize designs and ensure RTL and gate equivalence through formality checks is unmatched. You are a collaborative team player, ready to integrate IPs in SoCs/Subsystems and create RTL designs that meet customer needs. If you are ready to leverage your expertise in a role that shapes the future of semiconductor design, Synopsys is the place for you. What You'll Be Doing: Perform RTL Quality Signoff Checks such as LINT, CDC, and RDC. Understand design/architecture and develop timing constraints for synthesis and timing . Run preliminary synthesis to ensure desi...

You are a seasoned professional in RTL Design and Signoff , bringing a wealth of experience and expertise to the table. You have a keen understanding of the complexities of RTL Quality Signoff and are adept at proposing resource requirements to meet project goals. Your leadership skills are top-notch, allowing you to guide a team of engineers through various pre-silicon static verification activities on IPs/Subsystems . You have a strong grasp of design and architecture , enabling you to develop precise timing constraints for synthesis and timing . Your ability to ramp up on new RTL Design and Static Verification tools and methodologies using Synopsys Products ensures that you stay ahead of ...

You are a highly experienced and motivated professional with a solid background in SoC RTL Design . With over 12 years of experience , you have honed your skills in RTL Design, Lint, CDC, RDC, Synthesis, and Constraints Development . You possess a deep understanding of design concepts, ASIC flows, and stakeholder management . Your technical expertise allows you to debug and diagnose violations and errors, set up flows and methodologies for RTL Signoff tools, and develop timing constraints . You are an effective leader, capable of managing and growing a team, providing continuous feedback, and improving the quality of deliverables . Your excellent communication skills help you interact with c...

You are a highly motivated and experienced ASIC Digital Design Engineer with a strong background in digital design for high-speed serial interfaces . You have a deep understanding of USB, PCIe, Ethernet, Display, and HDMI protocol standards , and you thrive in a collaborative environment. Your expertise in Verilog RTL design, microarchitecture, and timing constraints development makes you a valuable asset to any team. You are adept at using tools like Spyglass for CDC/RDC/Lint and have excellent debugging skills. Your ability to propose and implement design updates based on various requirements, coupled with your experience in test coverage and physical design timing closure , sets you apart...

What You ll Need: EE graduate from a reputed school, with post-graduate qualifications preferred. 15+ years of industry experience in RTL design or verification using simulation-based technologies. 5+ years of experience managing medium to large-sized teams. In-depth understanding of Assertion-based verification using formal and simulation methods. Strong knowledge of hardware design (Verilog/VHDL) and micro-architecture. Expertise in Unix/Linux automation shell (bash, csh) and scripting (Tcl, Perl, Python). Excellent oral and written communication skills. Expertise in one or more areas such as Formal Property Verification testbench development, floating point arithmetic operations, C/C++, I...

Description We are seeking a highly skilled ASIC Physical Design, Sr Staff Engineer to join our team in India. In this role, you will be responsible for the physical design and implementation of high-performance ASICs, collaborating closely with cross-functional teams to ensure successful project delivery. Responsibilities Design and implement physical layouts for ASIC designs. Conduct place and route activities to meet timing and area requirements. Perform timing analysis and optimization to ensure high-performance ASICs. Collaborate with RTL designers to ensure design feasibility and manufacturability. Utilize EDA tools for physical design tasks such as Cadence, Synopsys, or Mentor Graphic...

What You ll Be Doing: Manage and lead a team of 7-8 SoC/Subsystem RTL Design Engineers for various customer engagements. Work with Synopsys customers to understand their needs and define RTL Signoff and design scope and activities. Lead the team to perform various RTL Design and Signoff activities for SoC Subsystems such as SoC u-Architecture and Integration, RTL Design (Verilog/SystemVerilog), Lint, CDC, RDC, Synthesis, Constraints Development. Assist and mentor the team in day-to-day activities and grow the capabilities of the RTL Design team for future assignments. Review various results and reports to provide continuous feedback to the team and improve the quality of deliverables. Report...

Description We are seeking a Staff ASIC RTL Digital Design Engineer to join our dynamic team in India. The ideal candidate will have a strong background in ASIC design and will be responsible for developing high-quality RTL designs, participating in verification processes, and collaborating with multiple teams to ensure successful project completion. Responsibilities Design and implement RTL code for ASIC digital circuits. Perform RTL simulations and verification using tools like ModelSim or VCS. Collaborate with verification engineers to ensure design functionality and performance. Participate in design reviews and provide constructive feedback. Work closely with physical design teams to en...

Working on Functional Verification of High-Speed PHY IPs for DDRxx, LPDDRxx, PCIex, Display, and HDMI protocol standards. Studying IP/design blocks/Firmware Specifications and building/updating verification plans and test cases. Building/updating functional verification environments to execute test plans. Developing DV/Firmware test benches, test plans, and test cases. Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs). Performing simulation, random and focused stimulus generation, and coverage analysis. Collaborating closely with digital designers for debugging and achieving desired coverage. Developing architecture a...

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are an experienced and motivated SOC Engineer with a passion for cutting-edge technology and innovation With a strong background in system-on-chip (SOC) design and verification, you bring a wealth of knowledge and a keen eye for detail You thrive in a collaborative environment, working seamlessly with cross-functional teams to deliver high-quality solutions Your problem-solving skills are exceptional, and you have a proven track record of successfully managing complex ...

What You ll Need: MS/Ph.D. in Computer Science, Computer Engineering, or Electrical Engineering. 15+ years of experience in software development and testing large C++ applications in Linux. Expertise in RTL Simulation andemulation/prototyping. Ability to understand and solve complex technical problems. Experience with runtime performance improvements and benchmarking.

We are looking for a passionate and self-driven individual to join the NES SOC architecture team and to help define and build NEX SoC(s) for Intel Server, Client and IoT platforms.Your responsibilities will include, but are not limited to:definition, specification and analysis of a family of Interconnects for use with Intel and ARM architecture based SoC(s).- Analysis of IP bandwidth, latency requirements and define SOC Coherent and Non-coherent interconnect.- define interconnect topology- Analysis of workloads and partitioning to determine candidates for coherent and non-coherent interconnect choices.- Performance modeling and Analysis Qualifications: Behavioral traits that we are looking f...

Introduction As a Hardware Developer at IBM, youll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in todays market. Your Role and Responsibilities : We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBMs microprocessor chip design team. As a member of functional DFT team ( Power on Reset, Architecture Verification Program, Array BIST teams ), you will be required but n...

12+ years of experience in ASIC design Proficient in Verilog coding, RTL design and complex control path and data path designs Knowledge of any of the interface Protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display, Ethernet, SATA Knowledge of RTL checks ex- LINT, SDC, CDC Familiar with synthesis flow, LEC and timing constraints Experience in writing Verilog testbench and running simulations.

Role: RTL Design Engineer Experience: 10+years Notice Period: Max 15days preferred Role Overview We are looking for a RTL Design Engineer? to deploy andsupport our front-end tools, to develop scripts to automate regression anddebug flows, and to work along with our design, implementation and verificationteams. What you'll do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools Identify and priori...

Autodesk Application Engineer with AEC expertise to support clients with Revit, AutoCAD, Civil 3D, Navisworks, and BIM 360/ACC. Duties include pre-sales demos, tech support, training, and optimizing BIM workflows. Key Responsibilities: Support and maintain EDA tools and CAD environments used in RTL design, simulation, synthesis, and verification. Develop and maintain automation scripts to streamline CAD workflows (Python, Shell, Perl, TCL). Collaborate with design, verification, and software teams to resolve tool-related issues and enhance productivity. Interface with EDA vendors to resolve technical issues, evaluate tool updates, and provide feedback. Manage license servers and monitor tool...

Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web-scale and service provider networks. Cisco's silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus (with an on-site gym, healthcare, caf, social interest groups, and philanthropy) with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Write micro-architecture specifications and participate in reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integra...

Cisco's silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus (with an on-site gym, healthcare, caf, social interest groups, and philanthropy) with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Write micro-architecture specifications and participate in reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integration and timing methodology/analysis. Develop and analyze functional coverage. Help define, evolve, and support our design methodology. ...

Candidate will be responsible for building/maintaining highlyconfigurable and reusable IO Subsystems (Note: An IO Subsystem is alogic IP that processes the IO Pads/IO Ring information and requiredlogic to allow multiple on-chip peripherals to share the same IOs in aconfigurable manner) Job Description In your new role you will: Candidate will be responsible for building/maintaining highlyconfigurable and reusable IO Subsystems (Note: An IO Subsystem is a logic IP that processes the IO Pads/IO Ring information and requiredlogic to allow multiple on-chip peripherals to share the same IOs in aconfigurable manner) Candidate will be responsible for RTL design for integration of IO pads into SoC, ...

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL/Test Pervassive Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high p...

Alphawave Semi is looking for Senior Engineer I - ASIC Design to join our dynamic team and embark on a rewarding career journey. Analyze and assess problems. Apply quality principles and methodology in processes to enhance output. Assess new product designs to meet project and product requirements. Create engineering designs. Identify the design needs of clients. Manage disputes and conflicts. Manage product design and development to meet project and product requirements. Oversee Workplace Safety and Health Systems (WSH) for the company.