477 Rtl Coding Jobs - Page 19

Role Purpose The purpose of the role is to design, and architect VLSI and Hardware based products and enable delivery teams to provide exceptional client engagement and satisfaction. Do Define product requirements, design and implement VLSI and HARDWARE Devices. Constant upgrade and updates of design tools, frameworks and understand the analysis of toolset chain for development of hardware products. Ability to analyse right components and hardware elements to choose for product engineering or development. Ability to conduct cost-benefit analysis and choose the best fit design. Knowledge on end to end flow of VLSI including design, DFT and Verification and Hardware product development from design, selection of materials, low level system software development and verification. Needs by displaying complete understanding of product vision and business requirements Develop architectural designs for the new and existing products Part Implementation of derived solution Debug and Solve critical problems during implementation Evangelize Architecture to the Project and Customer teams to achieve the final solution. Constant analysis and monitoring of the product solution Continuously improve and simplify the design, optimize cost and performance Understand market- driven business needs and objectives; technology trends and requirements to define architecture requirements and strategy Create a product-wide architectural design that ensures systems are scalable, reliable, and compatible with different deployment options Develop theme-based Proof of Concepts (POCs) in order to demonstrate the feasibility of the product idea and realise it as a viable one Analyse, propose and implement the core technology strategy for product development Conduct impact analyses of changes and new requirements on the product development effort Provide solutioning of RFPs received from clients and ensure overall product design assurance as per business needs Collaborate with sales, development, consulting teams to reconcile solutions to architecture Analyse technology environment, enterprise specifics, client requirements to set a product solution design framework/ architecture Provide technical leadership to the design, development and implementation of custom solutions through thoughtful use of modern technology Define and understand current state product features and identify improvements, options & tradeoffs to define target state solutions Clearly articulate, document and sell architectural targets, recommendations and reusable patterns and accordingly propose investment roadmaps Validate the solution/ prototype from technology, cost structure and customer differentiation point of view Identify problem areas and perform root cause analysis of architectural design and solutions and provide relevant solutions to the problem Tracks industry and application trends and relates these to planning current and future IT needs Provides technical and strategic input during the product deployment and deployment Support Delivery team during the product deployment process and resolve complex issues Collaborate with delivery team to develop a product validation and performance testing plan as per the business requirements and specifications. Identifies implementation risks and potential impacts. Maintain product roadmap and provide timely inputs for product upgrades as per the market needs Competency Building and Branding Ensure completion of necessary trainings and certifications Develop Proof of Concepts (POCs), case studies, demos etc. for new growth areas based on market and customer research Develop and present a point of view of Wipro on product design and architect by writing white papers, blogs etc. Attain market referencsability and recognition through highest analyst rankings, client testimonials and partner credits Be the voice of Wipros Thought Leadership by speaking in forums (internal and external) Mentor developers, designers and Junior architects for their further career development and enhancement Contribute to the architecture practice by conducting selection interviews etc Mandatory Skills: RTL coding.Experience: 8-10 Years.

Short Description Good in RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture Hands on experience in PCIe/DDR/Ethernet Hands on experience inI2C,UART/SPI Hands on experience inSpyglass Lint/CDC / Synopsys DC / Verdi/Xcellium scripting languages like Make flow, Perl ,shell, python Mandatory Skills: ASIC Design.Experience: 5-8 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Physical Place and Route. Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Physical Place and Route. Experience: 3-5 Years.

Responsibilities Understand the standards/specifications Architecture development and documenting implementation level details Hands on work for every aspect of verification cycle Responsible for the compliance with the latest Methodologies. Developing Verification IPs Define Functional Coverage matrix and Comprehensive Test plan Regression management and functional coverage closure DUT integration and verification for IP delivery sign-off Leading small team Person Specification Required Skills Hands-on experience of complete verification cycle with strong verification concepts Strong knowledge of Verilog, SystemVerilog and UVM Experience in UVM based Verification IP development Experience in AMBA AXI/AHB/APB System buses Hands on work experience on any of PCIe/Eth/USB/DDR etc. Hands on experience with System Verilog Assertions Scripting for automation, release process, simulations, regressions Good command over written and oral communication Desirable Skills Lead the Verification IP development with 2 or more junior engineers Exposure to full verification cycle Desired Skills and Experience DV Engineer, Design Verification, Verification Engineer

Required Skills Experience in Logic design / RTL coding is a must. Experience is SoC design and integration for complex SoCs is a must. Experience in Verilog/System-Verilog is a must. Experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint and CDC. Experience in Synthesis / Understanding of timing concepts is a plus. Experience in ECO fixes and formal verification. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture. Excellent oral and written communications skills. Proactive, creative, curious, motivated to learn and contribute with good collaboration skills.

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Job Responsibilities : You will develop RTL code to implement FPGA-based digital designs , working from specification stage through to system integration. Projects will range from Mid to multi-million gates. Most projects include designing logic for latest generation of high speed serial protocols like PCIe gen5, Gen6, USB 3.2 Ethernet 10G/25G/100G, digital signal processing and control logic (bus interfaces and state machines) Understand the customer requirements and product definition Define architecture and detailed design spec based on requirements and various trade-offs Micro-architecture and coding of assigned module in VHDL/Verilog Write test bench for verifying design for complete scenario coverage Implementation of the design for porting on FPGA after required optimization based on available resources and timing closure requirement FPGA debugging and HW/SW integration Requirements: 6+ years of experience, including successful completion of FPGA based projects Coding experience in VHDL and/or Verilog is must Experience targeting Xilinx and/or Altera FPGAs required Familiarity with tools like Modelsim, Questasim, Xilinx Vivado, Planahead, Altera Quartus etc. is required Familiarity with debugging tools like Chipscope, Signal Tap, Logic analyzer, Scope, FPGA editor Implementation of designs with multiple clock domains is required Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed Experience in RTL implementation of DSP algorithms will be appreciated Experience in development of PCIe, USB, Ethernet transceivers, DDRx, ADC, DAC, AMBA-AXI, SRAM, USB, UART, I2C, SPI will be appreciated

Job Responsibilities : You will develop RTL code to implement FPGA-based digital designs , working from specification stage through to system integration. Projects will range from Mid to multi-million gates. Most projects include designing logic for latest generation of high speed serial protocols like PCIe gen5, Gen6, USB 3.2 Ethernet 10G/25G/100G, digital signal processing and control logic (bus interfaces and state machines) Understand the customer requirements and product definition Define architecture and detailed design spec based on requirements and various trade-offs Micro-architecture and coding of assigned module in VHDL/Verilog Write test bench for verifying design for complete scenario coverage Implementation of the design for porting on FPGA after required optimization based on available resources and timing closure requirement FPGA debugging and HW/SW integration Requirements: 6+ years of experience, including successful completion of FPGA based projects Coding experience in VHDL and/or Verilog is must Experience targeting Xilinx and/or Altera FPGAs required Familiarity with tools like Modelsim, Questasim, Xilinx Vivado, Planahead, Altera Quartus etc. is required Familiarity with debugging tools like Chipscope, Signal Tap, Logic analyzer, Scope, FPGA editor Implementation of designs with multiple clock domains is required Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed Experience in RTL implementation of DSP algorithms will be appreciated Experience in development of PCIe, USB, Ethernet transceivers, DDRx, ADC, DAC, AMBA-AXI, SRAM, USB, UART, I2C, SPI will be appreciated

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -12+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Verify different functions/Components of the Server Processor chip, Memory BIST or Reset Flow and Boot Firmware. Work with logic and development teams to identify test scenarios, create test plans and execute the scenarios. Create/Update the test environment and code automated test scenarios and environments. Work with development and system tests team to ensure coverage criteria is met. Create/Update formal verification rules for various functions in PCIe and PIPE specification. Develop skills in IBM Functional verification tools and apply them successfully. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5+ years of experience in pre-silicon functional verification 3+ years of experience in Memory BIST or Reset Flow/Boot Firmware Good understanding of the hardware development cycle for the product. Expertise in Object Oriented Programming concepts using C++/System Verilog to design and develop reusable functional verification components Good Understanding of VHDL or Verilog, and able to trace the source of unexpected design behaviour through to RTL source. Track record of defining new approaches to verification that are adopted by others and progress the state of the art of verification within a team. Expertise in automation language, tool and scripts – Python/Perl Experience in test automation. Analytical skills, decision making ability and attention to details . Ability to work in a team, under schedule pressure and maintain deadlines Development experience with Linux / Unix Experience in Test Plan creation and develop test cases from the requirements & Design Documents, reviews, reports creation. Strong communication skills and passionate to work well as part of a team. Preferred technical and professional experience Stress testing and ability to identify corner case scenarios. Good understanding of computer system architecture and microarchitecture. Knowledge in Standard IO protocols ( I2C, SPI and other serial interface) Knowledge of PHY Verification Knowledge in IP Integration and SoC Knowledge in Server boot Flow Knowledge in Secure boot Firmware

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-6years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Verify different functions/Components of the Server Processor chip, Memory BIST or Reset Flow and Boot Firmware. Work with logic and development teams to identify test scenarios, create test plans and execute the scenarios. Create/Update the test environment and code automated test scenarios and environments. Work with development and system tests team to ensure coverage criteria is met. Create/Update formal verification rules for various functions in PCIe and PIPE specification. Develop skills in IBM Functional verification tools and apply them successfully. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8+ years of experience in pre-silicon functional verification 3+ years of experience in Memory BIST or Reset Flow/Boot Firmware Good understanding of the hardware development cycle for the product. Expertise in Object Oriented Programming concepts using C++/System Verilog to design and develop reusable functional verification components Good Understanding of VHDL or Verilog, and able to trace the source of unexpected design behaviour through to RTL source. Track record of defining new approaches to verification that are adopted by others and progress the state of the art of verification within a team. Expertise in automation language, tool and scripts – Python/Perl Experience in test automation. Analytical skills, decision making ability and attention to details . Ability to work in a team, under schedule pressure and maintain deadlines Development experience with Linux / Unix Experience in Test Plan creation and develop test cases from the requirements & Design Documents, reviews, reports creation. Strong communication skills and passionate to work well as part of a team. Preferred technical and professional experience Stress testing and ability to identify corner case scenarios. Good understanding of computer system architecture and microarchitecture. Knowledge in Standard IO protocols ( I2C, SPI and other serial interface) Knowledge of PHY Verification Knowledge in IP Integration and SoC Knowledge in Server boot Flow Knowledge in Secure boot Firmware

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL/Test Pervassive Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -8+ years of relevant experience - At least 1 generation of processor core/cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: Semiconductor Integration.Experience: 3-5 Years.

We are seeking an experienced System on Chip (SoC) Architect to join our development team. The ideal candidate will be involved in designing, integrating, and optimizing SoC hardware architectures and ensuring seamless software-hardware co-development. You have: Bachelors Degree in Electrical Engineering, Computer Engineering, or a related field (Masters or Ph.D. preferred). Overall,15+ years of experience as a Chip design expert. 8+ years of proven experience in IC design, SoC architecture, or a similar role. Proficiency in hardware description languages: Verilog, VHDL, and System Verilog Expertise in EDA tools for IC design and verification: Mentor Graphics, Cadence, or Synopsys Strong understanding of SoC architecture, including processor, memory subsystem, and interconnects (e.g., AXI, AMBA). Experience with hardware-software co-design and debugging tools. Knowledge of low-power design techniques and methodologies. Strong scripting skills in Python, Tcl, or Perl for automation. Tools : MATLAB/Simulink, Microsoft Visio, Mentor Graphics QuestaSim It would be nice if you also had: Familiarity with high-level modeling tools like SystemC. Knowledge of advanced packaging technologies (e.g., Chiplets, 3D ICs). Exposure to machine learning or AI accelerators in SoC design. Develop SoC architectures for advanced applications, ensuring scalability, performance, and power efficiency Lead hardware design and integration processes, including RTL coding, synthesis, and verification Collaborate with software teams to ensure efficient software-hardware co-design and integration Perform system-level modeling and simulations to validate architectural choices Guide SoC implementation, including floor planning, physical design, and timing closure Follow best practices for IC design and manufacturing Analyze system requirements, identify bottlenecks, and propose innovative solutions

Overview Developing emulation testbenches to support necessary DV scenarios and firmware/software/hardware bring up Responsibilities Build emulation models from RTL and release/support those models Develop emulation tools such as debugger and monitor features Work closely with verification and software development teams Develop emulation and verification strategy Develop test framework and test cases Write documents such as verification specification and reports Coach younger colleagues Emulation and Prototyping technologies such as Palladium, Veloce, Zebu, HAPS, (these names are registered trade marks of their respective owners) Requirements Experience - minimum 15+ yrs and above with minimum of 5+ yrs of experience of woking on any one of the Emulation platform. Education QualificationBE/BTech

This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; - Grade Specific Focus on Electrical, Electronics Semiconductor. Entry level graduate with limited commercial and technical work experience. Build skills and expertise in a chosen Engineering Discipline. Works to instructions and directions and delivers reliable results. Keen to understand clients business needs. Solves routine problems. Organises own time with a short time horizon. Skills (competencies)

This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; - Grade Specific Focus on Electrical, Electronics Semiconductor. Entry level graduate with limited commercial and technical work experience. Build skills and expertise in a chosen Engineering Discipline. Works to instructions and directions and delivers reliable results. Keen to understand clients business needs. Solves routine problems. Organises own time with a short time horizon. Skills (competencies)

This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs), printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment. Focus on Electrical, Electronics and Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers.

This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs), printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment. Focus on Electrical, Electronics and Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers.

Requirements roject Aurix 3G/RC1- Ethernet Engineer Purpose Service Provider to provide Register-transfer level ( RTL ) Design and Verification services for Infineon project (s). Service Results (including Scope of Work & Deliverables) Deliver all Service Results necessary for achieving the Purpose and in accordance with the Statement of Work, including but not limited to: System-On-Chip design and verification of complex SoC, including verification content planning and execution, test case creation and maintenance. ISO26262 functional safety verification of automotive products including fault simulation and documentation of results. RTL coding for modules or SoC. Documentation of work and results according to Infineon s practise in project archive including archiving of document design data, change requests, application notes and lessons learnt. To keep Infineon updated on Service performance and immediately notify Infineon in the event of any technical problems or foreseeable delays. Service Requirements Service Provider shall maintain ownership over work packages of SoC verification for a dedicated module/subsystem/chip, including: Verification planning. Drive review of verification plan with design and concept engineering. Implementation or adaptation of SoC test cases according to plan. RTL & gate-level simulation / signoff including functional and code coverage closure Test suite quality assurance using e.g. Certitude tools. Debug of test failures in RTL & gate-level simulations. Issue/bug tracking including driving for closure with concept and design engineering. RTL design using the Very High Speed Integrated Circuit Hardware Description Language ( VHDL ). Coding, High Speed Ic, Rtl Design, Vhdl

MTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to microarchitect , design and deliver data fabric IP RTL . These include new and existing features and components for AMD s data fabric IP , working in close coordination with verification to ensure design quality. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Digital design implementation and micro-architecture of components of the Infinity Data Fabric Micro-architecture and RTL coding in Verilog/SystemVerilog of Data fabric components and its features as the fabric scales for server, data center application systems. Responsible for the inter IP integration issues resolution Design flow quality checks - Lint, CDC, RDC and others Timing closure - timing constraints, synthesis, logic-depth reduction Design area optimizations Low power design techniques, UPF included PREFERRED EXPERIENCE: 6 to 10 years of working experience in ASIC design Proficiency in Verilog/SystemVerilog RTL Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification. Active knowledge of ASIC design quality flows Knowledge of cache coherency and /or fabric /NOC design is a plus Low power analysis and design Version control systems such as Perforce, Git ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-BM2

MTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to microarchitect , design and deliver data fabric IP RTL . These include new and existing features and components for AMD s data fabric IP , working in close coordination with verification to ensure design quality. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Digital design implementation and micro-architecture of components of the Infinity Data Fabric Micro-architecture and RTL coding in Verilog/SystemVerilog of Data fabric components and its features as the fabric scales for server, data center application systems. Responsible for the inter IP integration issues resolution Design flow quality checks - Lint, CDC, RDC and others Timing closure - timing constraints, synthesis, logic-depth reduction Design area optimizations Low power design techniques, UPF included PREFERRED EXPERIENCE: 6 to 10 years of working experience in ASIC design Proficiency in Verilog/SystemVerilog RTL Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification. Active knowledge of ASIC design quality flows Knowledge of cache coherency and /or fabric /NOC design is a plus Low power analysis and design Version control systems such as Perforce, Git ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-BM2

About Marvell . Your Team, Your Impact Marvell Compute and Custom Solutions has been at the forefront of developing and delivering leading edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast-growing product lines, Marvell technology is powering the next-generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Datacenter market segments. The proliferation of the data economy is accelerating and creating significant strains on the global data infrastructure. Built on decades of expertise and execution, Marvell s custom ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide-array of flexible business models. What You Can Expect Design, develop, implement, verify, and document micro-architecture and RTL for complex designs in the networking domain with strong focus on Ethernet. Work closely with system and chip architects to design high-quality, zero-defect and A0 implementations. Participate in the full design development cycle, end-to-end, from writing micro-architecture docs, RTL coding, specifications of timing, closely work with design verification teams to review test plans and execution of test, ability to bring up block tests on silicon during lab testing, and maintenance of designed blocks and reusable IPs. Produce comprehensive block uArchitecture and register Specs. Schedule detailed reviews with cross-functional teams Evaluate and participate in improving design and verification methodologies. Supervise or mentor other digital design engineers. What Were Looking For Bachelor s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience. Master s degree in Computer Science, Electrical Engineering or related fields with 10-12 years of experience. PhD in Computer Science, Electrical Engineering or related fields with 8-10 years of experience. Creating micro-architectural specs from standards, architectural specifications. System Verilog RTL coding with System Verilog Assertions. Creating modular/reusable design components. Ability to multi-task and must be flexible and adaptable to a rapidly changing and demanding environment. Demonstrated success in project leadership. Experience in the following areas is MUST: Ethernet - low speed and High speed, MacSec, Networking Domain Low power design. High speed designs Strong passion to drive and work on cutting-edge enhancements in Ethernet and hyper scalers. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1