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5.0 - 9.0 years
0 Lacs
karnataka
On-site
You will be working at Samsung Semiconductor India Research (SSIR), which is one of the largest R&D centers outside Korea for Samsung Electronics. Your role will involve: - Good Experience in Top/Block, FLAT/Hier DFT insertion flow methodologies - Executed scan & MBIST insertion, ATPG and verification at full chip level - Experience in timing closure in DFT modes - understanding of shift, capture timing constraints, MBIST constraints and their impacts - Generate, review and validate DFT constraints to achieve timing closure of high-speed design - Experience in timing closure in DFT modes, RTL analysis, logic synthesis, physical design, signoff verification (STA, Formality, Simulations) - Exp...
Posted 2 days ago
6.0 - 8.0 years
0 Lacs
bengaluru, karnataka, india
On-site
Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, IP integration, Extraction, Physical Verification, and taking blocks to the closure. Job Description In your new role you will: Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, IP integration, Extraction, Physical Verification, and taking blocks to the closure. Design Application Engineering (DAE) will be responsible for supporting project teams using Infineon Design System (Flows, Design Package & Design assistance). You will be the first point o...
Posted 1 month ago
6.0 - 8.0 years
0 Lacs
bengaluru, karnataka, india
On-site
Working experience in Physical Design implementation areas including Synthesis, LEC, and PnR as well as good exposure to signoff areas, particularly power, timing, and IR signoff. Job Description In your new role you will: Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, IP integration, Extraction, Physical Verification, and taking blocks to the closure. Design Application Engineering (DAE) will be responsible for supporting project teams using Infineon Design System (Flows, Design Package & Design assistance). You will be the first point of contact for project teams in case of issues and will...
Posted 1 month ago
6.0 - 8.0 years
0 Lacs
bengaluru, karnataka, india
On-site
Working experience in Physical Design implementation areas including Synthesis, LEC, and PnR as well as good exposure to signoff areas, particularly power, timing, and IR signoff. Job Description In your new role you will: Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, IP integration, Extraction, Physical Verification, and taking blocks to the closure. Design Application Engineering (DAE) will be responsible for supporting project teams using Infineon Design System (Flows, Design Package & Design assistance). You will be the first point of contact for project teams in case of issues and will...
Posted 2 months ago
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