Head Embedded NVM Technologies Theron Solutions

5.0 - 9.0 years

0 Lacs

gujarat

On-site

You should have an M.S or PhD in Electrical Engineering, Materials Science or equivalent field. You must possess a strong understanding of CMOS and eNVM device physics, process modules, yield improvement, failure mechanisms, and analytical techniques (physical and electrical). A deep understanding of key eNVM technologies such as charge trap, floating gate, RRAM, MRAM, etc is essential. Experience in technology parameters and figures of merit like bit cell size, macro size, endurance, retention, power, latency, mask count, etc is required. You should have a proven track record in delivering these technologies into volume manufacturing and achieving competitive performance. The ability to lead cross-functional teams and ensure project completion within timeline and cost targets is necessary. Working across different cultures and geographies should be a strength along with being a good team player. Having an innovative and competitive mindset will be beneficial in this role.,

Posted 4 days ago

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eNVM Bitcell Layout Design Engineer / Lead Tata Electronics

5.0 - 10.0 years

0 Lacs

gujarat

On-site

You are a skilled embedded non-volatile memory (eNVM) Bitcell Layout Design Engineer / Lead interested in joining the eNVM team at Tata Electronics Private Limited (TEPL) to lead the development and optimization of eNVM bitcells. In this role, you will be responsible for designing layout and implementing eNVM bitcells across a wide range of Foundry CMOS technologies, from 130nm to 28nm, including BCD and advanced FinFET technology nodes. Your work will contribute to building high-yield, high-performance memory IP for various applications in automotive, IoT, and mobile markets. To excel in this position, you should ideally have 5-10 years of experience in the semiconductor industry with expertise in memory bit cell and array layout. A background in microelectronics, semiconductor physics, or related fields (Bachelors, Masters, or PhD) is preferred. Proficiency in using EDA tools such as Cadence or Calibre for layout design, including verification by DRC and LVS, is essential. Additionally, knowledge of memory bit cells and arrays like SRAM, MRAM, RRAM, components included in PDK, and experience with bench measurement would be advantageous. Your responsibilities will involve designing eNVM bitcell layout (eFuse, eFlash, RRAM, MRAM) across various foundry processes, creating, optimizing, and verifying bitcell kits, conducting root cause analysis of device and bitcell issues, driving infrastructure improvement for bitcell kit and SLM creation, evaluating foundry PDK changes, and collaborating with design & layout teams to fix violations. Moreover, you will work with diverse engineering teams in different geographic locations and time zones, provide advice on ESD & latch-up prevention techniques, and contribute to indigenous IP development and filing disclosures. For the lead position, strong leadership skills with experience in mentoring and motivating high-performing teams are expected. Effective communication and collaboration across global, cross-functional groups, adaptability to diverse environments, curiosity, resilience, data-driven problem-solving, humility, innovation, and agility are desirable attributes for this role. If you are passionate about driving innovation in eNVM bitcell layout design and keen on contributing to the development of cutting-edge semiconductor products at Tata Electronics, we welcome you to apply for this exciting opportunity.,

Posted 2 weeks ago

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Non-Volatile Memory IP Design Manager NXP Semiconductors

12.0 - 16.0 years

0 Lacs

karnataka

On-site

The Non-Volatile Memory Design Manager role within the CTO/Frontend Innovation/NVM Design Department at NXP involves overseeing the deployment of embedded Non-Volatile Memory solutions across the organization's business and product lines. This includes integrating Logic NVM, Flash, and advanced memory technologies like RRAM and MRAM. By implementing innovative NVM technologies, the team gains a competitive edge in the market. As the Design Manager for NXP's NVM design group in Bangalore, India, you will lead the expansion of the team and drive alignment among a group of talented engineers. Your primary responsibility is to ensure that the team delivers innovative NVM IP to create differentiating products effectively. Key Responsibilities: - Build and lead a team of 10 to 20 engineers specializing in NVM Analog Design, Digital Design, and Verification. - Define and oversee the deployment of Logic NVM, Flash, and Disruptive Memory Solutions (RRAM, MRAM). - Manage resource allocation and planning in collaboration with design management and project leads. - Drive the technical vision for cost-effective, fast time to market, and risk management for NVM IP. - Ensure compliance with design flow and quality standards while identifying opportunities for improvement. - Foster a high-performance culture within the team through performance management processes. - Develop relationships with business partners, foundries, and 3rd party collaborators. Qualifications: - BE or MS in Electrical/Electronics Engineering with 12+ years of design experience. - Proven leadership experience within an engineering team. - Strong communication skills and international relationship management abilities. - Hands-on expertise in digital, analog, and mixed-signal design and verification. - Specific knowledge in NVM design and architectures is preferred. - Proficiency in quality-managed design flows, tools, and methodologies. - Experience in launching high volume mixed-signal products, especially in the automotive market. This position offers an exciting opportunity to drive innovation and lead a team of engineers in developing cutting-edge NVM solutions to support NXP's product lines and business objectives.,

Posted 1 month ago

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