Design Verification Engineer ACL Digital

5.0 - 7.0 years

0 Lacs

hyderabad, telangana, india

On-site

#ACL Digital is hiring: IP Verification Engineer UVM Verification We are looking for engineers with strong SystemVerilog UVM, behavioral modeling, and system-level performance verification experience. Hands-on expertise in AXI4, NoC protocols, and multi-master/multi-slave configurations is required. Experience with DRAM memory controllers, traffic patterns, bandwidth & latency analysis is a plus. Proficiency with VCS/Questa/Xcelium/Riviera and Vivado debug is essential. Experience: 57 years Notice Period: 030 days

Posted 20 hours ago

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Senior Design Verification Engineer ACL Digital

5.0 - 7.0 years

0 Lacs

hyderabad, telangana, india

On-site

IP Verification Engineer UVM verification Experience : 5-7 years Location : Hyderabad System Verilog based UVM Functional verification, Behavioral modelling of functional blocks. System level performance verification, traffic patterns, bandwidth & latency analysis. Expertise in AXI4 bus protocol. Experience in Network On Chip (NOC) protocol. Experience in multi-master, multi-slave AXI4 use-case configurations. Knowledge of DRAM memory controllers. Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging. Setup verification environment and bring up simulations with various simulations such as VCS / Qu...

Posted 3 days ago

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