8 Rdl Jobs

The successful candidate will be responsible for developing and maintaining applications using Python, SQL, Reactjs, and Java. You will also be involved in building and managing data pipelines on platforms such as Databricks, DBT, Snowflake, RSL (Report Specification Language-Geneva), and RDL (Report Definition Language). Your experience with non-functional aspects like performance management, scalability, and availability will be crucial. Additionally, you will collaborate closely with front-office, operations, and finance teams to enhance reporting and analysis for alternative investments. Working with cross-functional teams, you will drive automation, workflow efficiencies, and reporting enhancements. Troubleshooting system issues, implementing enhancements, and ensuring optimal system performance to follow the sun model for end-to-end coverage of applications will also be part of your responsibilities. Qualifications & Experience: - Education: Bachelor's degree in Computer Science, Engineering, or a related field. - Experience: Minimum of 2 years of experience in enterprise software development and production management, preferably within financial services. - Proficiency in at least one programming language - Python, Java, Reactjs, SQL. - Familiarity with alternative investments and their reporting requirements. - Hands-on experience in relational databases and complex query authoring. - Ability to thrive in a fast-paced work environment with quick iterations. - Must be able to work out of our Bangalore office. Preferred Qualifications: - Knowledge of AWS/Azure services. - Previous experience in asset management/private equity domain. This role provides an exciting opportunity to work in a fast-paced, engineering-focused startup environment and contribute to meaningful projects that address complex business challenges. Join our team and become part of a culture that values innovation, collaboration, and excellence. FS Investments: 30 years of leadership in private markets FS Investments is an alternative asset manager focused on delivering attractive returns across private equity, private credit, and real estate. With the recent acquisition of Portfolio Advisors in 2023, FS Investments now manages over $85 billion for institutional and wealth management clients globally. With over 30 years of experience and more than 500 employees across nine global offices, the firm's investment professionals oversee a variety of strategies across private markets and maintain relationships with 300+ sponsors. FS Investments" active partnership model fosters superior market insights and deal flow, informing the underwriting process and contributing to strong returns. FS is an Equal Opportunity Employer. FS Investments does not accept unsolicited resumes from recruiters or search firms. Any resume or referral submitted without a signed agreement is the property of FS Investments, and no fee will be paid.,

You will be joining a team at Qualcomm Asia Pacific Pte. Ltd. focused on RF Front End Modules for the Cellular and Wireless Data markets. As a senior technical specialist, you will provide leadership in the development of new technology platforms using your expertise in materials, device physics, and processes. This role requires working closely with multiple product development teams within the Business Unit Engineering organization. Your responsibilities will include collaborating across different functions in a dynamic environment, supporting the development of advanced technologies for backend interconnect, passivation, packaging, and singulation. You will be involved in improving existing processes to enhance efficiency, product reliability, and yield. Additionally, your role will require expertise in process integration, photolithography techniques, and backend processes. You will play a crucial role in developing industry-leading design guidelines, conducting Design of Experiments (DOE), and supporting the integration of advanced technologies for RF-SiP applications. Moreover, you will lead technology integration efforts, perform technical risk assessments, and ensure product reliability metrics are met. To qualify for this position, you should have a Master's Degree in Mechanical, Materials, or Chemical Engineering, with a preference for a PHD. A minimum of 10 years of experience in electronics packaging, especially in the RF module industry, is desired. Strong technical understanding of semiconductor packaging materials, industry standards, and quality management is essential. Excellent communication skills, willingness to travel internationally, and the ability to collaborate with cross-functional teams are crucial for success in this role. If you are an individual with a disability and require accommodations during the application process, Qualcomm is committed to providing accessible support. Qualcomm is an equal opportunity employer and expects its employees to adhere to all applicable policies and procedures. Staffing and recruiting agencies are advised not to submit unsolicited resumes or applications for this role. For further information, please reach out to Qualcomm Careers.,

As a highly experienced Siemens Opcenter Technical Architect, you will be responsible for leading the design, integration, and optimization of Opcenter solutions within our manufacturing and PLM landscape. Your deep expertise in Siemens Opcenter MES, APS, Quality Management, and RD&L modules, along with your proven experience in integrating Opcenter with Teamcenter and SAP PLM, will be essential in ensuring seamless data flow, operational efficiency, and strategic alignment across our enterprise systems. With over 8 years of hands-on experience in Siemens Opcenter and a strong understanding of manufacturing operations, LIMS, CALVIN, PLM, and ERP systems like SAP, you will play a critical role in architecting and implementing MES, APS, Quality Management, and RD&L modules. Your expertise in integration technologies such as web services, APIs, and middleware will enable you to integrate Opcenter with other systems effectively. Your core responsibilities will include leading the design, configuration, and customization of Siemens Opcenter solutions, ensuring alignment with enterprise architecture and business goals. You will also be responsible for integrating Opcenter with Teamcenter and SAP PLM, optimizing manufacturing and lab processes, and collaborating with cross-functional teams to provide technical leadership and mentorship. Preferred qualifications for this role include experience with Opcenter RD&L, LIMS, and CALVIN for lab workflow management, strong analytical and problem-solving skills, as well as excellent communication and stakeholder management abilities. Overall, as an Opcenter Technical Architect, you will be instrumental in driving efficiency, compliance, and automation within our systems while fostering collaboration and innovation across the organization.,

Opening for a IT SOFTWARE Company 1-mssql Server - Creating Tables, Stored Procedure, Function, Views, Index etc. 2-SSRS (Sql Server Reporting Services) - Creating new Reports, Formats in Tablix and matrix form. 3-Deploying rdl and rdlc reports to reports server or on given path as per requirement. 4-Client interaction if required. Please share me ur resume on neesha.shetty@efleetsystems.com Call me on 7021826056

We Are Hiring: Principal Engineers Chip Design (Back End / Front End / Analog IP/IC) Preferred Skills and Experience: Minimum 1+ years of experience in Project Management (Waterfall and Agile Hybrid methodology) Exposure to continuous improvement and cross-functional collaboration Educational Qualifications: Master's degree in VLSI Design from reputed institutes (IITs/NITs preferred) Bachelor's in Electronics and Communication or a related field 1. Job Title: Principal Engineer – Chip Design Back End Required Skills & Experience: Minimum 8+ years of strong experience in backend flows for MCU or low-power SoC designs Leadership experience with DFT, Physical Design, and Formal Verification teams Exposure to Frontend and Analog design processes Ability to collaborate effectively across functional teams Experience in product support during both pre- and post-production stages (including RMA support) 2. Job Title: Principal Engineer – Chip Design Front End Required Skills & Experience: Minimum 8+ years of experience in system architecture for ARM-based MCU product development Expertise in RTL design, RTL coding, and RTL integration Strong debugging and design capabilities Experience leading verification teams, including static and dynamic verification, test management (UPF, GLN, Test Modes) Familiarity with industry-standard EDA tools (e.g., Synopsys for LINT, CDC, SDC validation, and power analysis) Exposure to Backend and Analog design processes Cross-functional collaboration with PD, DFT, and STA teams for timing and power closure Experience in pre- and post-production product support and RMA handling 3. Job Title: Principal Engineer – Analog IP/IC Design Required Skills & Experience: Minimum 8+ years of experience in custom analog/mixed-signal IC design Proficiency in variation-aware design, verification planning, and analog layout parasitic extraction (LPE) Hands-on experience with analog/mixed-signal EDA tools (e.g., Cadence, Synopsys) Strong debugging and design validation skills Product support experience across development lifecycle, including RMA stage

Key Responsibilities: Serve as the Geneva SME (Tech) with a focus on technical and business aspects of Geneva RSL/RDL. Oversee the software development and delivery process, ensuring compliance with the Software Development Life Cycle (SDLC). Manage and lead the Change Release Cycle, coordinating with multiple teams to ensure seamless integration of new features, updates, and patches. Provide technical leadership, guidance, and support to the technology team, ensuring adherence to best practices and quality standards. Collaborate with business stakeholders to understand financial business requirements and translate them into effective technical solutions using the Geneva platform. Troubleshoot complex issues related to Geneva RSL/RDL and provide timely solutions. Ensure that all processes are aligned with organizational policies, regulatory requirements, and industry standards. Provide training and mentorship to junior team members, fostering their growth within the organization. Requirements: Strong experience and expertise in Geneva RSL/RDL. In-depth understanding of the Software Development Life Cycle (SDLC) and Change Release Cycle. Solid knowledge of financial business processes and ability to adapt technical solutions to meet business needs. Excellent leadership and team management skills with a proven ability to drive project success. Strong analytical, problem-solving, and troubleshooting abilities. Excellent communication and interpersonal skills. Bachelors or Masters degree in Computer Science, Information Technology, or a related field. Preferred Qualifications: Experience in the financial services industry or with financial products. Familiarity with Genevas integration with other systems or tools. Certification in relevant software development or project management methodologies (e.g., Agile, ITIL).

www.Sevyamultimedia.com About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia Sevya is an innovative semiconductor design company dedicated to pushing the boundaries of technology. We focus on developing cutting-edge solutions that empower the electronics industry. Our mission is to drive the future of technology, and we are seeking talented individuals to join our dynamic team. e About the job As ASIC Physical Design Lead you will be leading the design of IP/SoC in advanced process technologies, serving global Semiconductor product MNC clients. Job Summary: We are looking for an ASIC Physical Design Lead with extensive experience in timing closure and full-chip physical design. The candidate should be adept at interacting with the packaging team and managing tasks such as pads log, bump placement, and RDL routing. Key Responsibilities: Lead the physical design of complex ASIC projects from Netlist to GDSII. Perform timing closure tasks including synthesis, place and route, and static timing analysis. Oversee full-chip physical design processes, including floor planning, power grid design, clock tree synthesis, and signal integrity analysis. Collaborate with the packaging team to ensure seamless integration of the chip design with the package, including pads log management, bump placement, and RDL routing. Mentor junior engineers and guide them on physical design methodologies. Drive innovation and efficiency in physical design workflows. Qualifications: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. Minimum of 7 years of experience in ASIC physical design. Expertise in industry-standard EDA tools for physical design and verification. Strong understanding of timing closure techniques and challenges. Experience with full-chip design and familiarity with multi-voltage and multi-clock domain designs. Excellent problem-solving and analytical skills. Strong communication and leadership abilities. Why Join Us: Sevya is committed to creating an environment of innovation, professional growth, and collaboration. As an I/O Design Engineer, you will be a part of groundbreaking projects and a team that values creativity and excellence. We offer competitive compensation, benefits, and the opportunity to be a driving force in the future of semiconductor technology. If you are an ambitious Analog Design Engineer eager to push the boundaries of analog design and help shape the future of technology, we encourage you to apply. Join us in our mission to redefine what's possible in the world of electronics! Skills: Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

www.Sevyamultimedia.com Physical Design Manager / Senior Manager About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills SoC Design RTL Design, Integration, Lint/CDC/RDC, UPF IP/SoC UVM Verification PPA, Synthesis, Constraints Management Physical Design, Timing Closure, ECOs Sign-off - Timing, Power, EM/IR, DRC/LVS/ERC Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia ================ Physical Design Manager / Senior Manager #### **Job Summary:** We are seeking a highly experienced, hands-on and motivated Physical Design Manager/ Director to lead our physical design team. The ideal candidate will have extensive experience in block and top-level implementation, RDL/bump, pad location, EM/IR analysis, timing closure, physical verification closure, CAD flow bring-up, automation, planning, and estimation. This role involves managing complex design projects, leading a team of engineers, and ensuring the successful execution of physical design tasks from planning to tape-out. #### **Key Responsibilities:** - **Team Leadership:** - Lead, mentor, and manage a team of physical design engineers. - Foster a collaborative and innovative team environment. - Develop team skills through training and professional development initiatives. - **Project Management:** - Plan and estimate physical design tasks, resources, and schedules. - Track and report on project progress, ensuring timely delivery of milestones. - Coordinate with cross-functional teams, including design, verification, and packaging, to align physical design activities with project goals. - **Block and Top-Level Implementation:** - Perform and oversee block-level and top-level physical design implementation. - Ensure designs meet performance, power, area, and manufacturability requirements. - Perform detailed floorplanning, placement, and routing. - Constraints clean up, robustness of implementation - Timing feedback to design team and sign-off timing. - **RDL/Bump and Pad Location:** - Manage redistribution layer (RDL) and bump design for advanced packaging. - Optimize pad location for signal integrity and manufacturability. - **EM/IR Analysis and Timing Closure:** - Conduct electromigration (EM) and IR drop analysis to ensure robust power delivery. - Achieve timing closure through detailed static timing analysis (STA) and optimization. - **Physical Verification Closure:** - Perform physical verification (PV) closure, including design rule checking (DRC) and layout versus schematic (LVS). - Ensure designs comply with foundry and industry standards. - **CAD Flow and Automation:** - Develop and bring up CAD flows for physical design tasks. - Implement automation scripts to enhance efficiency and productivity. - **Continuous Improvement:** - Stay updated with the latest industry trends, tools, and methodologies in physical design. - Drive continuous improvement initiatives to enhance design processes and methodologies. - Implement best practices for physical design and contribute to the development of standards and processes. #### **Qualifications:** - **Education:** - Bachelors or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. - **Experience:** - 10-15+ years of experience in physical design, with at least 3 years in a managerial or leadership role. - **Technical Skills:** - Extensive experience in block and top-level physical design implementation. - Proficiency in RDL/bump design and pad location optimization. - Strong knowledge of EM/IR analysis and timing closure techniques. - Experience with physical verification closure (DRC, LVS). - Familiarity with CAD flow development and automation. - **Soft Skills:** - Excellent leadership and team management abilities. - Strong problem-solving and analytical skills. - Effective communication and interpersonal skills. - Ability to work in a fast-paced, dynamic environment and manage multiple projects simultaneously. #### **Preferred Qualifications:** - Experience with advanced node technologies (e.g., FinFET, SOI). - Knowledge of scripting languages (e.g., Python, Perl) for automation. - Experience with EDA tools such as Cadence, Synopsys, or Mentor Graphics. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"