3 Rdl Jobs

Key Responsibilities: Serve as the Geneva SME (Tech) with a focus on technical and business aspects of Geneva RSL/RDL. Oversee the software development and delivery process, ensuring compliance with the Software Development Life Cycle (SDLC). Manage and lead the Change Release Cycle, coordinating with multiple teams to ensure seamless integration of new features, updates, and patches. Provide technical leadership, guidance, and support to the technology team, ensuring adherence to best practices and quality standards. Collaborate with business stakeholders to understand financial business requirements and translate them into effective technical solutions using the Geneva platform. Troubleshoot complex issues related to Geneva RSL/RDL and provide timely solutions. Ensure that all processes are aligned with organizational policies, regulatory requirements, and industry standards. Provide training and mentorship to junior team members, fostering their growth within the organization. Requirements: Strong experience and expertise in Geneva RSL/RDL. In-depth understanding of the Software Development Life Cycle (SDLC) and Change Release Cycle. Solid knowledge of financial business processes and ability to adapt technical solutions to meet business needs. Excellent leadership and team management skills with a proven ability to drive project success. Strong analytical, problem-solving, and troubleshooting abilities. Excellent communication and interpersonal skills. Bachelors or Masters degree in Computer Science, Information Technology, or a related field. Preferred Qualifications: Experience in the financial services industry or with financial products. Familiarity with Genevas integration with other systems or tools. Certification in relevant software development or project management methodologies (e.g., Agile, ITIL).

www.Sevyamultimedia.com About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia Sevya is an innovative semiconductor design company dedicated to pushing the boundaries of technology. We focus on developing cutting-edge solutions that empower the electronics industry. Our mission is to drive the future of technology, and we are seeking talented individuals to join our dynamic team. e About the job As ASIC Physical Design Lead you will be leading the design of IP/SoC in advanced process technologies, serving global Semiconductor product MNC clients. Job Summary: We are looking for an ASIC Physical Design Lead with extensive experience in timing closure and full-chip physical design. The candidate should be adept at interacting with the packaging team and managing tasks such as pads log, bump placement, and RDL routing. Key Responsibilities: Lead the physical design of complex ASIC projects from Netlist to GDSII. Perform timing closure tasks including synthesis, place and route, and static timing analysis. Oversee full-chip physical design processes, including floor planning, power grid design, clock tree synthesis, and signal integrity analysis. Collaborate with the packaging team to ensure seamless integration of the chip design with the package, including pads log management, bump placement, and RDL routing. Mentor junior engineers and guide them on physical design methodologies. Drive innovation and efficiency in physical design workflows. Qualifications: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. Minimum of 7 years of experience in ASIC physical design. Expertise in industry-standard EDA tools for physical design and verification. Strong understanding of timing closure techniques and challenges. Experience with full-chip design and familiarity with multi-voltage and multi-clock domain designs. Excellent problem-solving and analytical skills. Strong communication and leadership abilities. Why Join Us: Sevya is committed to creating an environment of innovation, professional growth, and collaboration. As an I/O Design Engineer, you will be a part of groundbreaking projects and a team that values creativity and excellence. We offer competitive compensation, benefits, and the opportunity to be a driving force in the future of semiconductor technology. If you are an ambitious Analog Design Engineer eager to push the boundaries of analog design and help shape the future of technology, we encourage you to apply. Join us in our mission to redefine what's possible in the world of electronics! Skills: Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

www.Sevyamultimedia.com Physical Design Manager / Senior Manager About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills SoC Design RTL Design, Integration, Lint/CDC/RDC, UPF IP/SoC UVM Verification PPA, Synthesis, Constraints Management Physical Design, Timing Closure, ECOs Sign-off - Timing, Power, EM/IR, DRC/LVS/ERC Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia ================ Physical Design Manager / Senior Manager #### **Job Summary:** We are seeking a highly experienced, hands-on and motivated Physical Design Manager/ Director to lead our physical design team. The ideal candidate will have extensive experience in block and top-level implementation, RDL/bump, pad location, EM/IR analysis, timing closure, physical verification closure, CAD flow bring-up, automation, planning, and estimation. This role involves managing complex design projects, leading a team of engineers, and ensuring the successful execution of physical design tasks from planning to tape-out. #### **Key Responsibilities:** - **Team Leadership:** - Lead, mentor, and manage a team of physical design engineers. - Foster a collaborative and innovative team environment. - Develop team skills through training and professional development initiatives. - **Project Management:** - Plan and estimate physical design tasks, resources, and schedules. - Track and report on project progress, ensuring timely delivery of milestones. - Coordinate with cross-functional teams, including design, verification, and packaging, to align physical design activities with project goals. - **Block and Top-Level Implementation:** - Perform and oversee block-level and top-level physical design implementation. - Ensure designs meet performance, power, area, and manufacturability requirements. - Perform detailed floorplanning, placement, and routing. - Constraints clean up, robustness of implementation - Timing feedback to design team and sign-off timing. - **RDL/Bump and Pad Location:** - Manage redistribution layer (RDL) and bump design for advanced packaging. - Optimize pad location for signal integrity and manufacturability. - **EM/IR Analysis and Timing Closure:** - Conduct electromigration (EM) and IR drop analysis to ensure robust power delivery. - Achieve timing closure through detailed static timing analysis (STA) and optimization. - **Physical Verification Closure:** - Perform physical verification (PV) closure, including design rule checking (DRC) and layout versus schematic (LVS). - Ensure designs comply with foundry and industry standards. - **CAD Flow and Automation:** - Develop and bring up CAD flows for physical design tasks. - Implement automation scripts to enhance efficiency and productivity. - **Continuous Improvement:** - Stay updated with the latest industry trends, tools, and methodologies in physical design. - Drive continuous improvement initiatives to enhance design processes and methodologies. - Implement best practices for physical design and contribute to the development of standards and processes. #### **Qualifications:** - **Education:** - Bachelors or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. - **Experience:** - 10-15+ years of experience in physical design, with at least 3 years in a managerial or leadership role. - **Technical Skills:** - Extensive experience in block and top-level physical design implementation. - Proficiency in RDL/bump design and pad location optimization. - Strong knowledge of EM/IR analysis and timing closure techniques. - Experience with physical verification closure (DRC, LVS). - Familiarity with CAD flow development and automation. - **Soft Skills:** - Excellent leadership and team management abilities. - Strong problem-solving and analytical skills. - Effective communication and interpersonal skills. - Ability to work in a fast-paced, dynamic environment and manage multiple projects simultaneously. #### **Preferred Qualifications:** - Experience with advanced node technologies (e.g., FinFET, SOI). - Knowledge of scripting languages (e.g., Python, Perl) for automation. - Experience with EDA tools such as Cadence, Synopsys, or Mentor Graphics. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"