STA, Synthesis Wafer Space - An ACL Digital Company

4.0 - 8.0 years

0 Lacs

karnataka

On-site

You should have a strong understanding of EDA tools and flows, with specific experience in Tempus/Primetime. Your expertise should include timing closure (STA) and various timing closure methodologies. You will be responsible for pre/post-layout constraint development towards timing closure and collaborating with the design team to establish functional/DFT constraints. Additionally, you will need to integrate IP level constraints and define multi-voltage/switching aware corners. An understanding of RC/C model selection and expertise in abstraction techniques such as Hyperscale/ILM/ETM will be crucial for this role. You will also be expected to perform RC balancing and scaling analysis for fu...

Posted 1 month ago

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STA Lead ACL Digital

7.0 - 11.0 years

0 Lacs

karnataka

On-site

You should be well versed with timing closure (STA) and timing closure methodologies, along with the ability to develop pre/post-layout constraints for timing closure. You will be required to collaborate with the design team to establish functional/DFT constraints and integrate IP level constraints. Additionally, you should have experience in defining multi-voltage/switching aware corner definitions, selecting RC/C models, and possessing expertise in abstraction techniques such as Hyperscale/ILM/ETM. In this role, you will be responsible for conducting RC balancing and scaling analysis of full chip clocks as well as critical data paths. Proficiency in automation using PERL, TCL, and EDA tool...

Posted 2 months ago

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