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3.0 - 10.0 years
0 Lacs
bengaluru, karnataka, india
On-site
Job description In this role, you will be creating UVM testbenches for a SoC and IP, as well as tests, regressions, and functional coverage to achieve zero bug escapes. You will interface with the designers to develop the test plans, and from that develop testcases and coverage to thoroughly verify the RTL. Your regressions will grow to cover the full functionality of the design relative to the architectural simulator and will include corner case testing for the more challenging cases. Your test and coverage reviews will ensure key coverage. ESSENTIAL DUTIES AND RESPONSIBILITIES: Create UVM testbenches, tests, and constraints to ensure design correctness Design, develop, and maintain modular...
Posted 1 month ago
 
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