0.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Job Description: Job Description, As part of TLR team (top-level-route), R&D Engineer is primarily responsible for :- Place and Route, CTS, Routablity analysis with respect to congestion. Well versed in physical verification aspect, DRC, LVS, Antenna, LUP, ( chip finishing and Tapeout) Meeting RC requirements for manual/special signals Good understanding of calibre DRC/LVS/DFM,DFY, ERC and ESD latchup. Responsible for all the integrity checks (chip-finishing) and post Tapeout eJob view release, Good scripting knowledge perl and TCL, familiar with caliber, Innovus, Understanding of VLSI fabrication process, Implementing timing ECOs. Implementing IR drop fixes, RC extraction, signal EM fixes, ...

Posted 1 day ago

AI Match Score

Apply

Senior Physical Design Engineer Truechip

5.0 - 10.0 years

0 Lacs

hyderabad, telangana, india

On-site

Senior Physical Design Engineer Physical Design >> Senior Physical Design Engineer Post Senior Physical Design Engineer Required Experience 5 to 10 Years Location: Delhi NCR, Bangalore, Hyderabad Openings 8-10 Education BE/B.Tech./MS/M.Tech.(Electronics or Electronics & Communication) Physical Design Engineer knowledge of PD Flow from netlist to GDS (Floorplanning, Synthesis, Power Planning, Placement & Optimization, CTS, Routing, ECO steps, Timing/SI) Good idea about OCV/MMMC and multi power designs (Level shifters, Isolation cells etc) Should have worked extensively on XTalk/SI/EM Knowledge about CTS, Clock tree methodology and clock skewing. Tool specific knowledge: ICC, innovus, primetim...

Posted 3 weeks ago

AI Match Score

Apply

Low Power Formal Verification Aarna Hr Solutions

5.0 - 10.0 years

5 - 10 Lacs

Bengaluru, Karnataka, India

On-site

We are seeking a highly skilled Low Power Formal Verification Engineer to join our team. The ideal candidate will possess deep expertise in low power formal verification, advanced constraint development, and a strong understanding of timing analysis in complex SoC designs. This role is critical for ensuring the power efficiency and functional correctness of our designs through rigorous verification methodologies. Roles and Responsibilities: Utilize work experience in Advanced Constraint Verification & post-layout STA (Static Timing Analysis) . Apply expertise in Low Power Formal Verification techniques to ensure power efficiency and functional correctness. Demonstrate expertise in Constraint...

Posted 3 months ago

AI Match Score

Apply

Start Your Job Search Today

Browse through a variety of job opportunities tailored to your skills and preferences. Filter by location, experience, salary, and more to find your perfect fit.