ASIC RTL Design Engineer - Lead Engineer Evnek

10.0 - 15.0 years

12 - 17 Lacs

bengaluru

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Lead the architecture and RTL design of complex digital blocks and subsystems for ASICs or SoCs Develop RTL using Verilog/SystemVerilog to meet functional and performance specifications Review micro-architecture and provide design solutions optimized for power, performance, and area Work closely with the verification team to ensure thorough test coverage and efficient debugging Collaborate with synthesis, STA, and physical design teams for design closure

Posted 1 month ago

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Firmware Developer Kiash Solution

5.0 - 8.0 years

10 - 15 Lacs

Hyderabad

Work from Office

Considering candidates on LLM or firmware baremetal profiles with embedded domain Strong C, DS, Low Level Firmware/Baremetal Development Good to have Bootloader Dev Experience or Security Experience Exp in Embedded protocols (I2C, SPI, UART, Etc)

Posted 2 months ago

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ASIC RTL Design Engineer - Lead Engineer Evnek

10.0 - 15.0 years

12 - 17 Lacs

Bengaluru

Work from Office

Posted 3 months ago

AI Match Score

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