33 Process Technology Jobs

What You'll Be Doing: Designing and validating custom standard cells, including flip flops, clock gating cells, level shifters, and power gating cells. Optimizing standard cell circuits to achieve better performance, power, and area (PPA). Engaging in hands-on development while mentoring and coaching junior R&D engineers. Collaborating with layout designers to optimize layout parasitics and achieve target PPA. Involving in layout extraction and understanding layout-dependent parameters in the extracted netlist. Implementing, testing, and analyzing circuit design guidelines and methodologies. The Impact You Will Have: Driving innovations in standard cell design that contribute to the success of Synopsys products. Enhancing the performance, power, and area (PPA) of our silicon IP portfolio. Mentoring and developing the next generation of R&D engineers. Collaborating across functions to ensure methodology alignment and optimization. Contributing to the continuous improvement of circuit design methodologies. Supporting the integration of more capabilities into System-on-Chip (SoC) designs, meeting unique performance, power, and size requirements. What You'll Need: Bachelor's or Master's degree in Electrical Engineering or a related field. 10+ years of experience in standard cell library design. Deep understanding of CMOS device characteristics and submicron process nodes. Experience with FINFET/GAA technologies and high sigma variation analysis. Familiarity with layout design and optimization of layout parasitics. Who You Are: Strong analytical and logical skills. Effective communicator and collaborator. Proactive problem solver with a hands-on approach. Mentor and coach for junior engineers. Innovative thinker with a passion for technology.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. As a CPU Physical Design Methodology Engineer, you will work with implementation and CAD teams to implement the designs meeting aggressive power, area and performance goals using industry standard tools/flows for next generation CPUs. : Bachelor's/Masters degree in Electrical Engineering with 5+ years of practical experience Experience with Synthesis, place and route and signoff timing/power analysis. Knowledge of high performance and low power implementation techniques Proficiency in scripting (TCL, Python, Perl) Preferred qualifications Experience in deep submicron process technology nodes is strongly preferred. Knowledge of library cells and optimizations. Solid understanding industry standard tools for synthesis, place & route and tapeout flows. Good data analytical skills to identify and root cause physical design issues. Roles and Responsibilities Work with cross functional teams (RTL, Physical design, Circuits, CAD) to solve key physical design problems in CPU implementations. Develop innovative techniques in Physical design and optimization space to help meet aggressive PPA targets. Work with all external CAD tool vendors and internal CAD teams to identify and improve optimization issues related to CPU designs. Work with all block level implementation teams to analyze, implement and improve the optimization method as it pertains to the designs.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3 to 5 years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, And should be familliar to PNR tools like Innovus/FC Solid grip on STA fixing aspects to solve extreme critical timing and clock path analysis Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs and manual ECOs as well. Experience in deep submicron process technology nodes is strongly preferred - Below 10nm Knowledge of high performance and low power interface timing is added benefit. Strong fundamentals on basic VLSI design concepts, synchronous design timing checks, understanding of constraints Good experience with in Unix, TCL, PT-TCL, Tempus-TCL scripting Familiarity with Python background is added bonus

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. 5+ years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, GENUS, Innovus, ICC etc. Solid grip on STA fixing aspects to solve extreme critical timing bottleneck paths. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Additional Qualcomm Noida CPU team is hiring for developing high performance and power optimized custom CPU cores. Individuals to Handle hardening complex HMs from RTL to GDS [ Synthesis, PNR, Timing ]. We are excited to add folks with us for the most cutting-edge work. Here, individuals would have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world. Desired experience: 12+ years of experience in Physical design, STA. Solid understanding industry standard tools for physical implementation [ Genus, Innovus, FC, PT, Tempus, Voltas and redhawk]. Solid grip from floorplan to PRO and timing signoff along with understanding of IR drop and physical verification aspect. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: General Summary: Bachelors /Masters degree in Engineering Relevant experience of 2-12 yrs in any of the mentioned domain - Design/Verification/ Implementation Will be working on cutting-edge Wireless Technology (IEEE 802.11) team. Strong fundamentals in core areasMicroarchitecture, Computer Arithmetic, Circuit Design, Process Technology Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Design You will be responsible for developing HW blocks (IP design), conduct High/Mid/Low level Design review and delivery IP to Subsystem team for making complex SoCs. You will be a critical part of the WLAN subsystem, contribute to IP design, sign-off the core to the SOC design team. Strong communication skills to work with design teams worldwide Verification Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C As a design verification engineer you will work on developing IPs catering to upcoming Wifi standards like 802.11bn and beyond. You will have opportunity to contribute to the life cycle of the technology right from IP specification, till productization/customer deployments, leveraging your verification, pre and post silicon debug expertise. Implementation Candidate will be responsible for next generation WLAN hardmacro implementation Extensive experience in Synthesis (DC or Genus), Formal Verification (LEC / Formality), Conformal Low Power, PTPX, Primetime, Conformal ECO Extensive experience in UPF based power intent and synthesis

Experience 20+ years of experience in product development, operation, process optimization, and technology leadership roles partly or fully in Purified Isophthalic Acid (PIA) Exposure to Purified Isophthalic Acid (PIA) industry (operation + technical services / technology) is a must, preferably with hands on experience of converting a PTA plant to PIA. Key Responsibilities Stabilize PIA plant operation by addressing technology issues and achieve design plant rate, specific consumption norms and product quality. Develop and execute the technology strategy aligned with the business strategy Assess global competitiveness through benchmarking. Develop long-term and mid-term strategies to bridge gaps with top quartile / decile performance Plan, develop and drive improvement projects to ensure RIL assets remain competitive Support execution of capital projects and long term PIOs for flawless commissioning Foster functional excellence, ideate top-down radical improvements & drive long term PIOs Support Platform Initiatives to develop digital tools for improving productivity of plant including but not limited to Process Digital Twin, data driven models for problem solving, use of AI / ML for trouble shooting Establish best practices and standards to ensure consistency for safe, efficient and reliable operations. Build and mentor a high-performing technology team, fostering innovation and technical excellence. Engage with industry partners, research institutions, and government agencies to foster collaboration. Support business teams in assessing market trends, customer needs, and partnership opportunities. Core Competencies Deep domain knowledge in Purified Isophthalic Acid (PIA) process technology and thorough understanding of the challenges while converting a Purified Terephthalic Acid (PTA) plant to PIA including the corrosion aspects and steps needed to mitigate them. Fundamental understanding of PIA technology landscape – as-is and future. Ability to work with an entrepreneurial mindset. Strong program management, and stakeholder engagement skills. Experience with techno-economic analysis, lifecycle assessment, and sustainability evaluation. Strong leadership and team management capabilities

Job Role - Engineer CoE Sub-Functional Area - Aromatics & LAB Job Location - RCP, Navi Mumbai Job Accountabilities: Process & quality monitoring for Aromatics Technology Plants Identify and analyse deviations Perform root cause analysis Propose corrective action and track the status of process improvement Identify opportunities for profit improvement Identify opportunities for product quality enhancement Process design calculations for the improvement schemes Develop process design package using appropriate tools Participate in commercial plant trials Understand and evaluate basic engineering design documents Participate in plant performance audits as per set guidelines Participate in Critical PHAs and turnaround activities of the related plants Validate MoCs to ensure specified standards and codes are followed in calculations Support preparation of stage gate-2 and 3 document for Capital projects Participate in HAZOP of new projects Validate equipment data sheets prepared by engineering contractor Contribute to derive value from technology network Skills Required: Analytical ability for problem solving Programming exposure Knowledge of chemical engineering and process technology Ability to plan / discuss results and network under the guidance of a senior colleagues Process design calculations at Skill level Simulation skills Use of Six sigma for problem solving Good communication &management skills Result Orientation Key Attributes (Experience and Qualifications): Min. BE/B Tech in Chemical Engineering or Diploma in Chemical from a reputed institute Min. 3 years of experience.

Job Role - Technologist CoE Sub-Functional Area - Aromatics & LAB Job Location - RCP, Navi Mumbai Job Accountabilities: Process & quality monitoring for Aromatics Technology Plants Identify and analyse deviations Perform root cause analysis Propose corrective action and track the status of process improvement Identify opportunities for profit improvement Identify opportunities for product quality enhancement Process design calculations for the improvement schemes Develop process design package using appropriate tools Participate in commercial plant trials Understand and evaluate basic engineering design documents Participate in plant performance audits as per set guidelines Participate in Critical PHAs and turnaround activities of the related plants Validate MoCs to ensure specified standards and codes are followed in calculations Support preparation of stage gate-2 and 3 document for Capital projects Participate in HAZOP of new projects Validate equipment data sheets prepared by engineering contractor Contribute to derive value from technology network Skills Required: Analytical ability for problem solving Programming exposure Knowledge of chemical engineering and process technology Ability to plan / discuss results and network under the guidance of a senior colleagues Process design calculations at Skill level Simulation skills Use of Six sigma for problem solving Good communication &management skills Result Orientation Key Attributes (Experience and Qualifications): Min. BE/B Tech in Chemical Engineering from a reputed institute Min. 3 years of experience.

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. As a Physical Design Timing Engineer, you will work with microarchitecture, RTL design, CAD, block level and top level physical design teams to run, analyze timing and drive timing closure. Roles and Responsibilities Work with design and DFT teams to understand, implement and validate constraints. Run SOC timing runs at all hierarchies Analyze timing and work with RTL/DFT teams to facilitate logic changes required. Feedback to block level and top level physical design engineers on key fixes required for timing closure. Work with CAD team to implement timing infrastructure. Create ECOs from timing runs to help timing closure. Document and help with timing methodology definition Preferred qualifications MS degree in Electrical Engineering; 10 years of practical experience Experience in timing flows with industry standard tools. Experience in all aspects of timing closure for multi-clock domain designs. Experience in deep submicron process technology nodes is strongly preferred. Experience with STA on large SOC with multi-scenario timing closure. Experience with Timing ECO techniques and implementation. Knowledge of library cells and optimizations. Familiar with circuit modeling, transistor fundamentals and worst case corner selection. Solid understanding industry standard tools for synthesis, place & route and tapeout flows. Good communication skills to work with different teams to accurately describe issues and follow them through for completion. Experience in STA and timing closure of high-performance SOC designs in sub-micron technologies. Knowledge of all aspects of timing including noise, cross-talk and others. Knowledge of basic SoC architecture and HDL languages like Verilog.

Process Design and Optimization: Develop and refine processes for producing polymers, quality, and cost-effectiveness Troubleshooting and Problem-Solving: Identify and resolve issues related to equipment, materials, and providing timely solutions Required Candidate profile Candidates should have experience in Polymer industry

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. 5 to 10 years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, GENUS, Innovus, ICC etc. Solid grip on STA fixing aspects to solve extreme critical timing bottleneck paths. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Experience Required: 8+ years to 10+ Education: Btech/Mtech Electronics/Electrical engineering Skills/Experience: Experience in Analog Mixed-signal DDR/HBM IP layout and verification of high-speed digital layout and solid understanding of high speed signal Experience in managing the technical aspects of project execution, ensuring timely delivery maintaining high quality standards, Advanced understanding of Deep submicron effects and mitigation, Advanced tool usage, Advanced floorplanning techniques, understand digital flow, Advanced strategies, Solid understanding of CMOS and FinFET layouts and process technology in 28nm and smaller, Good understanding of ESD and latchup layout design considerations, Familiarity with ASIC physical design flow: LEF generation, Place & Route & understanding of top level verification flow, DRC/LVS, LPE, Good understanding of IO frame and pitch requirements, power rail routings, IO abutment rules and requirements, bondpad layout, EM and IR considerations, DFM, etc Scripting skills for layout automation is a plus Remote site interaction, layout co-ordination activities, ability to foster accountability and ownership through hands-on technical leadership, Excellent written and verbal communication skills in interactions with customers, and internal development teams, Responsibilities: High Speed DDR/HBM Layout design Lead the layout design, development and implement technical solutions, Provide subject matter expertise & technical leadership in High Speed design such as DDR/HBM, Work with DDR PHY team, package engineers and system engineers to meet design specs, Perform scheduling duties, Remote site interaction etc Work with local team to support critical layout and floorplanning requirements Coordination duties with other layout teams both in Bangalore and globally, to detail out layout activities and obtain layout deliverables This includes reviewing and quality checking from remote Layout teams, Strict flow adherence and policing of internal policies to secure schedules,

Alternate Job Titles: Senior Layout Design Engineer Analog Mixed-Signal Layout Engineer Staff Engineer, Layout Design We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a seasoned professional with over 6 years of experience in Analog Mixed-Signal layout and verification You possess a robust understanding of deep submicron effects and mitigation, advanced tool usage, floor-planning, and routing Your expertise extends to CMOS and FinFET layouts and process technology in 28nm and below You are familiar with the layout design flow, including top-level verification flow, DRC/LVS, LPE, and have a good grasp of basic ESD and latch-up layout design considerations You understand power routes, EM and IR considerations, and DFM You have exposure to Analog/Mixed Signal circuit layout (e-g , RX, TX, PLL) Your excellent written and verbal communication skills enable you to interact effectively with internal development teams You are passionate about technology and thrive in a collaborative environment where your skills contribute to groundbreaking innovations, What Youll Be Doing: Designing and verifying complex Analog Mixed-Signal layouts, ensuring high-quality and reliable IPs, Collaborating with cross-functional teams to optimize layout designs for performance and manufacturability, Utilizing advanced tools and methodologies to mitigate deep submicron effects, Conducting floor-planning, routing, and top-level verification, Ensuring compliance with DRC, LVS, LPE standards and addressing ESD and latch-up considerations, Optimizing power routes and addressing EM and IR considerations for robust designs, The Impact You Will Have: Enhancing the performance and reliability of our high-speed SerDes IPs and other critical components, Driving innovation in Analog Mixed-Signal layout design, contributing to cutting-edge technology developments, Ensuring seamless integration and functionality of our IPs in diverse applications, Improving design efficiency and manufacturability through advanced layout techniques, Contributing to the success of our product development lifecycle by delivering high-quality designs, Supporting our mission to lead in chip design and IP integration, shaping the future of technology, What Youll Need: 6+ years of experience in Analog Mixed-Signal layout and verification, Advanced understanding of deep submicron effects and mitigation techniques, Proficiency in using advanced layout design tools and methodologies, Solid understanding of CMOS and FinFET layouts and process technology in 28nm and below, Familiarity with layout design flow, including top-level verification flow, DRC/LVS, LPE, Who You Are: You are detail-oriented, methodical, and have a deep understanding of layout design principles Your ability to communicate effectively and work collaboratively with cross-functional teams is exceptional You are proactive, always looking for innovative solutions to complex problems, and your passion for technology drives you to stay updated with the latest industry trends and advancements, The Team Youll Be A Part Of: You will be part of a dynamic and innovative team focused on developing high-performance Analog Mixed-Signal layouts Our team collaborates closely with other engineering departments to ensure the seamless integration and functionality of our IPs We value creativity, continuous learning, and a collaborative spirit to push the boundaries of technology and innovation, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

PURPOSE OF THE ROLE To execute operational plans for both established and novel product/technology projects by evaluating new technologies, offering suggestions for process improvement based on benchmarking analyses, and aiding in pilot activities and plant trials, in order to, enhance operational efficiency, safety, and product innovation, in alignment with RIL's Technology Strategy, central procedures, and guidelines, ensuring the organization's commitment to excellence and strategic growth KEY RESPONSIBILITIES - Participate in identifying opportunities for process improvements, assisting in achieving higher capacities - Participate in root cause analyses to understand intricate process and engineering challenges and support in providing recommendations - Support Sr Technologist in the identification and definition of enhancements and upgrades in current processes, equipment, and technologies, aiming to achieve higher production capacities and enhanced process efficiencies - Assist in implementing improvement projects to ensure alignment with technology strategy and operating plan - Support Senior Technologists in evaluating catalysts, chemicals, and additives, contributing to the optimization of processes and product quality - Collaborate in conducting pilot studies and scaled-up implementations, contributing valuable insights for technological advancements - Collaborate with R&D teams to facilitate scale-up and plant-level trials. Manage pilot studies, ensuring adherence to milestones, and provide inputs for successful scaled-up integration - Execute commercial plant trials, validating emerging technologies, and overseeing the seamless transition from laboratory testing to full-scale production - Perform simulations and APC models to optimize processes, enhance efficiency, and proactively address potential challenges - Create quarterly product performance benchmarking reports and translate insights into actionable recommendations KNOWLEDGE AND COMPETENCIES Education Qualifications - Bachelors or Master’s degree in Chemical Engineering Experience - 4-8 years of relevant industry experience in process technology, chemical engineering, in Refining or Petrochemical Industry FUNCTIONAL COMPETENCIES - Knowledge of product technology & advancement - Knowledge of latest tools & simulation studies - Knowledge of product development - Knowledge of application of science & engineering principles - Knowledge of Modelling Standards, Project Standards, and Project Execution Standards - Knowledge of Plant HSE use cases - Process Optimization - Innovation Management

Overview Main Purpose To lead formulation development of specific products under the Beverages platform and deliver successful productivity linked projects against the innovation agenda under India BU Carbonated Beverage portfolio significantly meeting applicable Regulatory, Operations and Commercial targets. Responsibilities Accountabilities Lead appropriate product development lab work, including timely development of bench-top prototypes, implementation and maintenance of stability testing, and support scale-ups for commercialization under JDs & New products under beverages Lead the flavour development program for R&D Beverages with appropriate learnings in flavour tools and techniques to ensure quality , speed and cost of flavour work with Flavour partners Collaborate with Nutrition and Regulatory functions and accurately implement guardrails and targets in advance of project delivery . Display advanced level of understanding in these areas Collaborate with International and local experts / Institutions on processes, quality challenges , best practices and document/share New Technology and techniques on beverage processing and leads implementation of best practices developed elsewhere Employ experimental design and statistical processes to provide robust formulation support by conceptualizing and preparing laboratory/pilot beverages and concentrates and adequately iterating on product attributes basis analytical and sensory evaluation Rigorously implementing basic Project management tools in all areas of product development work Integrate Consumer test results with key product deliverables and provide technical guidance and bench development for targeted development initiatives Ensure accurate processes for preparation, sampling and codification for analytical and sensory evaluations and interpretation of results Ensure clear work prioritization and action plans for self and DR (TBD) basis changing business strategies and establish responsibilities for cross functional support areas and monitor progress. Excellent communication skills both written and verbal , including documenting work/ programs accurately and timely into appropriate formats ( eg. laboratory notebooks) Utilization of interpersonal skills to work effectively within teams and cross-functions including International PD teams Job Dimensions what is the scope of the role volume, net revenue, budget, geography, number of customers, number of sites etc. for this role?This role involves : Leading product formulations for a wide spectrum of beverages Applying best in class tools and techniques - from a COE perspective Support significant CSD portfolio growth by Innovations Support an annual productivity program Qualifications Key Skills/Experience Required Experience and Qualification B. Tech., M. Tech., M.Sc. pHD in a Food Science & Technology or related scientific field (Biotechnology/ Microbiology etc.) with 8-10 years experience A proven track record in product development in R&D Knowledge & Experience Advanced knowledge of Formulation development techniques including Design of Experiments and Statistical applications Experience of working in FMCG sector essential with advanced knowledge of food science, Process technology, and good understanding of Nutrition and Regulations Stage Gate process Creative ability and ability to provide thought leadership on tactical aspects of projects Outstanding team working and excellent communication skills Ability to accurately analyze and communicate implications of experimental results Skills and Behavioral Attributes Good communication, interpersonal, influencing and persuasion skills Good project management and data interpretation skills Cross functional team-working Ability to reference and benchmark Main interactions within & outside organization Internal R&D Team Members Marketing & Innovation Marketing Operations/Quality Finance External Key Partners-Flavor Houses Key functional Partners Pkg/ Regulatory/ Category FOBO Partners Analytical Service Providers Lab Equipment/Consumables Vendors Key Challenges Ability to self-initiate, manage multi-tasking several projects (at least 5 on new Innovation + 5 on productivity ) running simultaneously and independently provide support manager to meet business objectives. Critically assess major risks in each project ( impacting product ) and evaluate and agree action plan with Manager Develop outstanding quality of product brief with clear targets and bench specified Development of superior and clearly differentiated products against project briefs that also meet the cost, quality and safety criteria besides having synergy with PepsiCo manufacturing platforms & beverages knowledge base Religiously document each development stream with raw and assessed data ( experiments and results) neatly parked with each milestone , actions and approvals captured and stored for posterity. Self-initiate and benchmark product development against available knowledge base worldwide for new products and technology platforms. Critical Competencies Proactively shares acquired information on Product science , technology , consumer trends etc , best practices across successful industries and ideas with others Creates an R&D work environment that makes work rewarding and enjoyable Strongly support R&C activities Quickly analyzes problems, develop accurate data and determine causes in each development stream of work Builds strong cross functional, internal and external partnership with technical experts and successfully leverage technical / functional expertise to solve critical product issues eg tap experts on critical ingredient functionality, emulsion technology and stabilization systems Demonstrates passion for mastering key business drivers ( Customer, Consumer, Competitor, cost and People) through in-depth and close collaboration with Insights, Mktg and Finance. Accurately implements customer / consumer oriented strategies and plans on Product development through effective use of Project management tools and techniques . Demonstrates functional / technical mastery of the current job Good time management and organization skills Excellent communication skills (verbal and written)

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3 to 5 years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, And should be familliar to PNR tools like Innovus/FC Solid grip on STA fixing aspects to solve extreme critical timing and clock path analysis Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs and manual ECOs as well. Experience in deep submicron process technology nodes is strongly preferred - Below 10nm Knowledge of high performance and low power interface timing is added benefit. Strong fundamentals on basic VLSI design concepts, synchronous design timing checks, understanding of constraints Good experience with in Unix, TCL, PT-TCL, Tempus-TCL scripting Familiarity with Python background is added bonus

Job Title COE/Automation Testing Q4-25 Responsibilities Writing effective, scalable code from scratch,.Integrating applications with third-party web services/APIs,.Developing back-end components to improve responsiveness and overall performance,.Integrating user-facing elements into applications/server-side logic,.Testing and debugging applications to ensure low-latency and high-availability,.Improve functionality of existing systems,.Accommodating various data storage solutions,.Implement security and data protection solutions,.Assess and prioritize feature requests,. Technical and Professional Requirements: Good experience in program managing of product functional and non functional testing.Knowledge of JIRA, Playwright, Selenium, Jmeter, API testing tools and Agile methodologyExcellent collaborative skillsKnowledge of Automation framework and tools, estimationKnowledge of JIRA, Playwright, Selenium, Jmeter, Parasoft toolsExcellent communication skillsKnowledge of Automation framework, Java, Typescript, PythonTools- Selenium, Playwright, Jmeter, parasoft Preferred Skills: Process->Testing processes->Test Automation Process Technology->Agile Management->Agile Management Tools->JIRA Educational Requirements Bachelor of Engineering Service Line Global Delivery * Location of posting is subject to business requirements

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. As a Physical Design Timing Engineer, you will work with microarchitecture, RTL design, CAD, block level and top level physical design teams to run, analyze timing and drive timing closure. Roles and Responsibilities Work with design and DFT teams to understand, implement and validate constraints. Run SOC timing runs at all hierarchies Analyze timing and work with RTL/DFT teams to facilitate logic changes required. Feedback to block level and top level physical design engineers on key fixes required for timing closure. Work with CAD team to implement timing infrastructure. Create ECOs from timing runs to help timing closure. Document and help with timing methodology definition Preferred qualifications MS degree in Electrical Engineering; 10 years of practical experience Experience in timing flows with industry standard tools. Experience in all aspects of timing closure for multi-clock domain designs. Experience in deep submicron process technology nodes is strongly preferred. Experience with STA on large SOC with multi-scenario timing closure. Experience with Timing ECO techniques and implementation. Knowledge of library cells and optimizations. Familiar with circuit modeling, transistor fundamentals and worst case corner selection. Solid understanding industry standard tools for synthesis, place & route and tapeout flows. Good communication skills to work with different teams to accurately describe issues and follow them through for completion. Experience in STA and timing closure of high-performance SOC designs in sub-micron technologies. Knowledge of all aspects of timing including noise, cross-talk and others. Knowledge of basic SoC architecture and HDL languages like Verilog.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 8 to 12 years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, GENUS, Innovus, ICC etc. Solid grip on STA fixing aspects to solve extreme critical timing bottleneck paths. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 2 to 5 years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, GENUS, Innovus, ICC etc. Solid grip on STA fixing aspects to solve extreme critical timing bottleneck paths. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. 5 to 7 years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, GENUS, Innovus, ICC etc. Solid grip on STA fixing aspects to solve extreme critical timing bottleneck paths. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3 to 5 years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, GENUS, Innovus, ICC etc. Solid grip on STA fixing aspects to solve extreme critical timing bottleneck paths. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 1 to 3 years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, GENUS, Innovus, ICC etc. Solid grip on STA fixing aspects to solve extreme critical timing bottleneck paths. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. As a Physical Design Timing Engineer, you will work with microarchitecture, RTL design, CAD, block level and top level physical design teams to run, analyze timing and drive timing closure. Roles and Responsibilities Work with design and DFT teams to understand, implement and validate constraints. Run SOC timing runs at all hierarchies Analyze timing and work with RTL/DFT teams to facilitate logic changes required. Feedback to block level and top level physical design engineers on key fixes required for timing closure. Work with CAD team to implement timing infrastructure. Create ECOs from timing runs to help timing closure. Document and help with timing methodology definition Preferred qualifications MS degree in Electrical Engineering; 10 years of practical experience Experience in timing flows with industry standard tools. Experience in all aspects of timing closure for multi-clock domain designs. Experience in deep submicron process technology nodes is strongly preferred. Experience with STA on large SOC with multi-scenario timing closure. Experience with Timing ECO techniques and implementation. Knowledge of library cells and optimizations. Familiar with circuit modeling, transistor fundamentals and worst case corner selection. Solid understanding industry standard tools for synthesis, place & route and tapeout flows. Good communication skills to work with different teams to accurately describe issues and follow them through for completion. Experience in STA and timing closure of high-performance SOC designs in sub-micron technologies. Knowledge of all aspects of timing including noise, cross-talk and others. Knowledge of basic SoC architecture and HDL languages like Verilog. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.