Job
Description
Lead the Design System Integration Tests Quality Assurance team, as a technical lead for qualifying various foundry and Infineon Design System (DS) (flows, methodologies, std-cells, io, mem, run-sets. models) across a diverse set of technology nodes ranging from 130nm to 22/12nm, in close collaboration with various stakeholders across multiple sites. This role that demands not just your technical prowess, but also your collaborative leadership style to steer multiple DSs QA along with flow, methodologies. You will act as the bridge between Design System (DS) development, product development, flow and methodologies, software architects to steer the product development cycle with high quality deliverables. In your new role you will: Qualifying the Infineon Design Packages (DP) components (set of std-cell, io, mem libraries, run sets) using the Infineon Design Flow (set of tools and methodologies). Ensuring high quality Design Systems deliverables by doing early full chip qualification environment and test a DP significantly before the dedicated Product line/test chip use them. Developing test plans, test-cases and executing test-cases to verify the integrity of major features for flow & library interfaces, changes across various tools, methodologies, and technologies. Alignment with design system(s)/flow teams, on integration level test topics and automation. Propose and implement test automation ideas to improve the turnaround time of test execution. Enhancement, addition, and maintenance of testcases, needed for qualifying the DP. Collaboration with various internal stakeholders, Business Line product team(s) to assure proper quality deliveries with adequate coverage. Having an overview and understanding of the relevant functional inter dependencies, trending software automation framework to improves execution efficiency. Establish and maintain test metrics and reporting. Working in compliance with all Infineon Quality/Process. Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, IP integration, Extraction, Physical Verification, and taking blocks to the closure. Analyze the results and any inconsistency issues to be reports via bug tracking system. Definition of new test-cases like product definition and for designing significant blocks of chip, including chip architecture and chip top integration, with the focus on improving Quality of Design System. Define and monitor key test metrics, build regression status reporting dashboard, Develop and execute QA test plans, verification methodology & test strategies for digital block/chip level to maximize the coverage of features/methodology supported in the technologies/Design Flows. Responsible for automation of manual processes (including design flow/design package qualification mechanisms, generation of test reports/dashboards etc.) and providing automation requirements for reducing manual steps in qualification. You are best equipped for this task if you have: A degree of BE/BTech (E&CE or Electrical) or ME/M.Tech (Electronics or VLSI) or equivalent 10+ year hands on experience in physical design, strong understanding in the RTL2GDSII flow design implementation in leading process technologies Insights into design/technology packages, design flow methodologies or Electronic Design Automation(EDA). Rich experience in leading medium size projects on SoCs medium size team. Know-how on automation tools like Jenkins. Git, DevOps is preferred. Knowing industry standard Software/Hardware QA practices & tools is highly desired. Experience working in multi-site teams. Clear verbal and written communication & presentation skills
