378 Primetime Jobs - Page 15

General Summary: NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work ...

5 to 7 years experience in both BW and Native HANA Good skills in SQL and ABAP Well versed in Data warehousing concepts Expertise in both BW and ECC back end object development and support Extractors , experience using various SAP & other sources, ADSOs, Composite Providers, DSOs, info cubes, Multi providers, etc. Hands on and technical conceptswith focus on HANA modelling. Proficient in design & development of HANA models Calculation views, procedures, Table functions Shift timings : 2 PM to 11 PM

We are looking for a skilled Physical Design Engineer with 5 to 10 years of experience to join our team at SILCOSYS Solutions Pvt. Ltd, located in the Design industry. Roles and Responsibility Develop and implement physical design flows and methodologies to ensure high-quality designs. Collaborate with cross-functional teams to identify and prioritize design requirements. Perform thorough analysis and verification of physical designs to ensure compliance with industry standards. Optimize design performance, power consumption, and area utilization through innovative techniques. Provide technical guidance and mentorship to junior engineers on best practices and design principles. Participate i...

Job Role Analyze and evaluate GPU architecture/microarchitecture and workload for performance and power optimizations GPU power modeling and estimation for projection and correlation GPU workload analysis, profiling, and characterizations Analyze, model, and minimize GPU register, logic, memory, and clock power Develop and maintain tests for pre-silicon and post-silicon power verifications. Work closely with multiple teams such as RTL designer, architecture, design verification, compiler, driver, silicon implementation, and post-silicon teams Knowledge of Graphics architecture is a plus Additional Job Description Preferred Qualifications: Master's or PhD degree or equivalent in Computer Engi...

About The Role Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Physical Design Good to have skills : NAMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will engage in a dynamic work environment where you will analyze, design, code, and test various components of application code across multiple clients. Your typical day will involve collaborating with team members to ensure the successful implem...

About The Role Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Physical Design Good to have skills : NAMinimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will engage in a dynamic work environment where you will analyze, design, code, and test various components of application code across multiple clients. Your day will involve collaborating with team members to ensure the successful implementation...

About The Role Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Physical Design Good to have skills : NAMinimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, your typical day involves analyzing, designing, coding, and testing various components of application code across multiple clients. You will engage in maintenance and enhancement tasks, ensuring that the software remains efficient and effective. Coll...

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer ...

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer ...

Required skills: He/She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design engrs. Interface with front-end ASIC teams to resolve issues. Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques. Timing...

Role: Lead Physical Design Engineer COMPANY OVERVIEW: MosChip is a semiconductor and embedded system design company with a focus on Embedded, Turnkey ASICs, Mixed Signal IP, Semiconductor & Product Engineering and IoT solutions catering to Aerospace & Defence, Consumer Electronics, Automotive, Medical and Networking & Telecommunications. Required skills: He/She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She...

Role - Static Timings Analysis Experience - 5 - 7 years Employment type - Full - Time Work Mode - Hybrid Roles and Responsibilities - 1. STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. 2. Timing analysis, validation and debug across multiple PVT conditions using Tempus. 3. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. 4. Hands-on experience with STA tools - Tempus 5. In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling

Job Purpose "This position is open with Bajaj Finance ltd." To handle and provide solution for a transactional activities of field team and making sure the implementation of projects are end to end satisfying the requirement. Duties and Responsibilities 1.Resolving SFDC functions related issues 2.Resolving BRE level issues 3.Educating internal and field teams on issues due to training requirements 4.Constant observations on the issues raised by the field team 5.Raising regular IT request to resolve issues 6.Constant communication between IT and Product teams to identify the changes 7.Attending bi-weekly meetings with IT to find the bigger solution 8.Find solutions to the repetitive problems ...

Physical Deisgn Lead Location: Bangalore / Hyderabad / Pune Experience - 8+ YoE In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl. Must have hands-on experience on Synopsys/Cadence tools. (Innovus, ICC2, Primetime, PT-PX, Calibre). Well versed with timing constraints, STA and timing closure. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology no...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Role Description: This is a full-time on-site role for a Senior Lead Physical Design Engineer based in Hyderabad. The Senior Physical Design Engineer will be responsible for tasks related to physical design, physical verification, logic design, circuit design, and RTL design in the development of silicon products. Qualifications: He/She should be able to do block level PNR including PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Minimum of 7-15 years of exper...

Experience into STA and timing closure/signoff experience with PD domain skill-set/knowledge. Candidate should be able to understand the timing constraints, analyze design details, analyze timing reports from prepcts to postcts stages, in-depth concepts of 14nm technode STA analysis, DCD knowledge. Candidate is preferably expert in PT and Tempus tools. Education Requirements B. Tech / M. Tech (ECE) Shift General Work Week Monday to Friday Joining time Immediate to 90 Days

1. Solid experience in place & route flow (placement guidelines, clock-tree synthesis, routing, timing optimizations). 2. Experience on hierarchical designs and/or Low Power implementation is an advantage. 3. Experience on Synthesis, interfacing with RTL and implementation 4. Experience on Floorplan design, including placement of hard macros, congestion reduction techniques. 5. Experience on Static Timing Analysis related activities , parasitic extractions, sign-off requirements). 6. Knowledge of Physical Verification (DRC/LVS/DFM, chip finishing) is an added advantage

For sub system in high performance microprocessor design, you are responsible for Timing constraintmodelling given timing specification, generation, validation. Design timing data generation, validation, timing data analysis. Driving timing convergence across different timing corners , by working with logic, circuit, integration designers. Ensuring quality and efficiency in timing convergence. Engaging in automation of flow, data analysis. Required education Bachelor's Degree Required technical and professional expertise 5+ years of industry experience Hands on experience in static timing analysis, modelling timing constraints, setting up timing environment and timing runs, data analysis, ti...

He/She should be able to do block level / top-level floor planning, PG Planning, partitioning (for hierarchical designs) , placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks and be able to fix the violations . S hould have worked on 4 5nm , 28nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design eng inee rs. Interface with front-end ASIC teams to resolve issues. Excellent comm...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Must Have Skills Floor Planning/Innovus/Fusion Compiler Good to have Experience on programming in Tcl/Tk/Perl. Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Mandatory Skills: VLSI Physical Place and Route.Location- Bangalore/ Pune/ Hyderabad/ Kochi

Key Skills: Netlist to GDSII flow, CTS, timing closure DRC, LVS, PERC, ERC, Soft Checks Tools: Innovus, ICC, PrimeTime, Calibre, Redhawk Worked on 28nm & below nodes Strong debugging and custom routing skills.

SUMMARY Part-Time Weekend Job Join Leading Food & Beverage Industry Team in Bangalore Job Role: Weekend Supporting Staff Company: Food & Beverage Industry Location: Bangalore Work Locations: Lulu Mall (Rajajinagar) Phoenix Marketcity (Whitefield) Shift Timing: 12:00 PM 5:00 PM Work Days: Saturday and Sunday Estimated Monthly Earnings: 3,000 3,500 Work 4 5 hours and earn extra income every weekend Key Responsibilities: Support kitchen and floor staff Serve starters, beverages, and non-vegetarian items (including chicken) Maintain cleanliness in service and dining areas Ensure smooth dining operations Requirements: No prior experience required (orientation provided) Must be energetic, discipli...

Expectations/ Requirements: l Key account Manager is principally responsible for Signing New Logos/ Merchants/Brands from Large Enterprise / Corporate Accounts. l The BDM achieves these goals by creating Funnel and Closure of accounts. Superpowers/ Skills that will help you succeed in this role: l Adaptability: Attitude of optimism and can-do orientation with ability to think creatively and navigate successfully past barriers and obstacles l Focus through the Noise: Ability to tune out distractions to focus work on priority goals and tasks l Persuasion: Ability to present concepts, ideas and proposals in a manner that is perceived positively by and clearly resonates with intended audiences a...