6.0 - 10.0 years

0 Lacs

hyderabad, telangana

On-site

As a STA Synthesis Engineer at AMD, you play a crucial role in planning and executing the front-end implementation of IPs and ensuring their closure. Your responsibilities include ownership of synthesis, LEC, CLP, prelayout STA, and postlayout STA/Timing closure. You will collaborate with the design team and PNR teams, guiding team members on technical issues. Key Responsibilities: - Responsible for front-end implementation of IPs, including synthesis, LEC, CLP, prelayout STA, and postlayout STA/Timing closure - Collaborate with designers and PNR teams to achieve closure - Plan and execute tasks as per schedule, ensuring quality delivery for synthesis and timing closure - Debug and resolve t...

Posted 1 month ago

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Silicon Design Engineer AMD

6.0 - 8.0 years

0 Lacs

hyderabad, telangana, india

On-site

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiencesfrom AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challengesstriving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Toge...

Posted 1 month ago

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Synthesis Design Engineer Advanced Micro Devices, Inc

1.0 - 5.0 years

0 Lacs

hyderabad, telangana

On-site

As a Silicon Design Engineer 2 at AMD, your role is crucial in executing the front end implementation of sub-blocks or IP. You will be responsible for tasks such as synthesis, LEC, CLP, prelayout STA, and postlayout STA/Timing closure. Collaborating with the design team and PNR teams is essential to achieve closure and execute tasks as per schedule. Your key responsibilities include ensuring quality delivery for synthesis and timing closure, as well as debugging and resolving technical issues efficiently. The ideal candidate for this role should have experience in synthesis and timing closure, with additional experience in LEC and CLP being a plus. Handling blocks with complex designs, high-...

Posted 3 months ago

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