4 Power Optimization Jobs

Developing SignOff ECO optimization algorithms and heuristics. Debugging issues related to design loading and timing/power optimization. Striving for continuous improvements in QoR to achieve faster timing convergence with optimal power overhead. Collaborating with a team of engineers to develop technical solutions to complex problems. Communicating with product engineers to understand and define problem scope. Ensuring strict performance and quality requirements are met. The Impact You Will Have: Enhancing the performance and efficiency of PrimeClosure, the industry's first AI-driven signoff ECO solution. Contributing to the development of cutting-edge algorithms that optimize timing and power in chip design. Improving the overall quality and reliability of our products through rigorous debugging and testing. Driving innovation and continuous improvement in our engineering processes. Supporting customer success by resolving issues and implementing new features based on their feedback. Helping shape the future of AI-driven optimization in the semiconductor industry. What You'll Need: A degree in Computer Science or Electronics. 5+ years of experience in relevant field Strong analytical and problem-solving skills. Proficiency in C/C++ and Linux. Excellent communication and teamwork abilities. A passion for technology and innovation.

Description We are seeking a highly skilled ASIC Physical Design, Sr Staff Engineer to join our team in India. In this role, you will be responsible for the physical design and implementation of high-performance ASICs, collaborating closely with cross-functional teams to ensure successful project delivery. Responsibilities Design and implement physical layouts for ASIC designs. Conduct place and route activities to meet timing and area requirements. Perform timing analysis and optimization to ensure high-performance ASICs. Collaborate with RTL designers to ensure design feasibility and manufacturability. Utilize EDA tools for physical design tasks such as Cadence, Synopsys, or Mentor Graphics. Conduct DRC/LVS checks and ensure design compliance with specifications. Support the verification team in physical design verification activities. Participate in design reviews and provide feedback for design improvements. Skills and Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 2-7 years of experience in ASIC physical design or related roles. Strong knowledge of ASIC design flow and methodologies. Proficiency in using EDA tools for physical design (e.g., Cadence, Synopsys, Mentor Graphics). Experience with place and route, timing closure, DRC/LVS checks, and physical verification. Familiarity with scripting languages (e.g., Perl, Tcl, Python) for automation of design tasks. Understanding of semiconductor manufacturing processes and design for manufacturability (DFM). Strong problem-solving skills and attention to detail.

Physical Implementation activities for Subsystems whichincludes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strongexpertisein timing convergence of high frequency data-path intensive Cores and advanced STA concepts we'll versed with the Block levelPnRconvergence with Synopsys ICC2/ CadenceInnovusand timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issueswrtconstraints validation, verification, STA, Physical design, etc we'll versed withTcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills andgood communicationskills. Minimum Qualifications: Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.Bachelors/masters degree inElectrical/ElectronicEngineering from reputed institution 2-10years of experience in PhysicalDesign/Implementation

Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. Bachelors/ Masters with 10+ years Systems Engineering or related work experience Educational Requirements Bachelor's/Masters/ Doctorate degree in Engineering, Electronics & Communication Micro Electronics Information Systems, Computer Science, or related field. Individuals who possess skills/experience in one or more of the following are requested to apply: Preferred Qualifications: Areas of Expertise (the more the better): Working experience with Complex Embedded Systems, Mobile/ IOT/Auto domains preferred. Expertise in fields such as power performance use cases , system modeling, SOC Profiling, PPA tradeoffs, post silicon bring up, and product qual. Firm grasp of computer architecture and OS fundamentals Post Silicon System Validation of SOC Performance, Architecture Analysis and Feedback to future products. Analyzing the power-performance data for various CPU, GPU, AI workloads benchmarks Conducting detailed workload characterization and sensitivity analysis Develop and enhance analysis tools and instrumentation to assist in analysis, identifying performance gaps and optimization options CPU microarchitecture including cache, Latency, BW analysis, etc. Linux/Android kernel development, device driver development and Android architecture experience Collaborate with the architecture team on power-performance trade-off analysis as part of product definition. Power and/or performance optimization, CPU, SOC SW DCVS/DVFS Governors exposure Working experience at System level, Linux kernel internals system programming Collaborate with internal teams and external partners for analysis and optimizations Lab Hands-on: with Power Data Acquisition/DAQs, Oscilloscope, JTAGs, ARM Developer Studio exposure Exposure to ADB shell, shell scripts, Python scripts, Understanding of Linux/android systems , automation scripts/environment Exposure to Git, Jira, Android and QTI tools Good communication skills, presentation skills and should manage his/her tasks independently Acts as a tech lead on projects and owns the outcome of the project.