7 Power Optimization Jobs

NVIDIA is seeking a highly motivated Hardware Engineer to join our multifaceted and fast-paced Silicon Solutions Group! Artificial intelligence is changing the world significantly starting with the technologies used in our day to day lives, cars we drive, autonomous machines in agriculture farms & factories, smart cities and science & technology development activities. GPUs are providing spectacular speed ups to scientific and medical research, enabling the advancement of humanity like never before. There has never been a more exciting time to work in NVIDIA. As part of the Silicon Solutions Team, we architect and deliver groundbreaking solutions for productizing NVIDIA's chips into consumer, professional, server, embedded, mobile, and automotive markets. Silicon characterization, correlation to arch & design expectations, finalize product specifications, develop productization techniques and infrastructure around it is our day to day work. Dealing with challenges of the brand-new process node technologies is also included in the work profile. What You Will Be Doing As a Silicon Power engineer for NVIDIA's family of chips and products, you will analyze pre-production silicon in pioneering process technologies for performance, power, yield, and quality to define the world's fastest products. Perform test case execution, debug silicon issues related to correlation and functionality, generate high quality results and provide design feedback. Find creative solutions to sophisticated silicon and system level problems and be on the frontline to lead show-stopper bugs, in order to enable product shipment. Work alongside system architects, chip and board designers, software/firmware engineers, HW/SW applications engineers, process/reliability specialists, ATE engineers, product managers, sales, and operations in a dynamic & high-energy work environment to bring industry-defining products to market. Collaborate with cross-functional teams to craft essential next generation product features that are important for performance, power optimization, and power management. Collaborate to craft tools for post-silicon work, build post-silicon methodologies to characterize silicon power, correlate silicon behavior with simulation. What We Need To See BS with 5 years or MS with 3+ years of proven track record in the area of silicon characterization and productization. Excellent problem solving, collaborative, and interpersonal skills. Experience working with offshore teams preferred. Hands-on experience with silicon bring-up, frequency and power characterization, Tester to System correlation, lab tools (oscilloscopes, multimeters, DAQ). Deep understanding of product binning methods, optimization techniques, methods, trade-off analysis and tools for data analysis and statistics. Exposure to critical path analysis, power analysis, process technologies, transistor/device physics, silicon reliability and aging mechanisms. Background with power supply and substrate noise analysis and mitigation. Exposure to digital design, circuit analysis, computer architecture, BIOS, drivers, and software applications.

Key Responsibilities: Design, develop, and maintain Linux kernel power management features (suspend/resume, CPU idle, DVFS, runtime PM). Work closely with hardware and platform teams to enable low-power modes for embedded SoCs. Analyze and debug power-related kernel issues , system hangs, or wakeup failures. Modify or extend kernel subsystems (e.g., PM framework, cpuidle, cpufreq, thermal). Tune Device Tree entries and drivers to ensure correct power domain usage and clock gating. Use tools like ftrace, powertop, kernelshark, perf , and pm-qa to monitor power behavior and system activity. Contribute to kernel board support packages (BSPs) for new platforms. Ensure system stability and compliance with upstream or vendor kernel baselines. Required Skills & Experience: Strong experience with Linux Kernel internals , particularly in Power Management . Hands-on experience with C programming for kernel-space. Familiarity with Device Tree , platform drivers, clocks, and regulators. Good understanding of low-power states , SoC power rails, and clock domains. Proficient in debugging tools and techniques for kernel issues (e.g., ftrace, crash, serial logs). Experience working on ARM-based architectures (e.g., Cortex-A series). Exposure to git , kernel build systems (Make, Kconfig), and cross-compilation toolchains.

KEY RESPONSIBILITIES: Define product features and capabilities, close architecture, and micro-architecture requirements, drive technical specifications for SoC and IP blocks to meet those requirements, and provide technical direction to execution teams Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features, optimizing for performance and power Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements Knowledge sharing and other contributions to Platform & System Architecture As an overall product owner, responsible for architecture analysis and technical solutions for marketing/feature change requests Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign offs Support Post-Si teams for Product Performance, Power and functional issues debug/resolution PREFERRED EXPERIENCE: Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-system, Fabrics, CPU/GPU coherency, Multimedia, I/O subsystems, Clocks, Resets, Virtualization and Security Experience analyzing CPU, GPU or System-level Micro-Architectural features to identify performance bottlenecks within different workloads Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at architecture, logic design, and circuit levels Excellent communication, management, and presentation skills. Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies ACADEMIC CREDENTIALS: bachelors or masters degree in related discipline preferred

Developing SignOff ECO optimization algorithms and heuristics. Debugging issues related to design loading and timing/power optimization. Striving for continuous improvements in QoR to achieve faster timing convergence with optimal power overhead. Collaborating with a team of engineers to develop technical solutions to complex problems. Communicating with product engineers to understand and define problem scope. Ensuring strict performance and quality requirements are met. The Impact You Will Have: Enhancing the performance and efficiency of PrimeClosure, the industry's first AI-driven signoff ECO solution. Contributing to the development of cutting-edge algorithms that optimize timing and power in chip design. Improving the overall quality and reliability of our products through rigorous debugging and testing. Driving innovation and continuous improvement in our engineering processes. Supporting customer success by resolving issues and implementing new features based on their feedback. Helping shape the future of AI-driven optimization in the semiconductor industry. What You'll Need: A degree in Computer Science or Electronics. 5+ years of experience in relevant field Strong analytical and problem-solving skills. Proficiency in C/C++ and Linux. Excellent communication and teamwork abilities. A passion for technology and innovation.

Description We are seeking a highly skilled ASIC Physical Design, Sr Staff Engineer to join our team in India. In this role, you will be responsible for the physical design and implementation of high-performance ASICs, collaborating closely with cross-functional teams to ensure successful project delivery. Responsibilities Design and implement physical layouts for ASIC designs. Conduct place and route activities to meet timing and area requirements. Perform timing analysis and optimization to ensure high-performance ASICs. Collaborate with RTL designers to ensure design feasibility and manufacturability. Utilize EDA tools for physical design tasks such as Cadence, Synopsys, or Mentor Graphics. Conduct DRC/LVS checks and ensure design compliance with specifications. Support the verification team in physical design verification activities. Participate in design reviews and provide feedback for design improvements. Skills and Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 2-7 years of experience in ASIC physical design or related roles. Strong knowledge of ASIC design flow and methodologies. Proficiency in using EDA tools for physical design (e.g., Cadence, Synopsys, Mentor Graphics). Experience with place and route, timing closure, DRC/LVS checks, and physical verification. Familiarity with scripting languages (e.g., Perl, Tcl, Python) for automation of design tasks. Understanding of semiconductor manufacturing processes and design for manufacturability (DFM). Strong problem-solving skills and attention to detail.

Physical Implementation activities for Subsystems whichincludes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strongexpertisein timing convergence of high frequency data-path intensive Cores and advanced STA concepts we'll versed with the Block levelPnRconvergence with Synopsys ICC2/ CadenceInnovusand timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issueswrtconstraints validation, verification, STA, Physical design, etc we'll versed withTcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills andgood communicationskills. Minimum Qualifications: Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.Bachelors/masters degree inElectrical/ElectronicEngineering from reputed institution 2-10years of experience in PhysicalDesign/Implementation

Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. Bachelors/ Masters with 10+ years Systems Engineering or related work experience Educational Requirements Bachelor's/Masters/ Doctorate degree in Engineering, Electronics & Communication Micro Electronics Information Systems, Computer Science, or related field. Individuals who possess skills/experience in one or more of the following are requested to apply: Preferred Qualifications: Areas of Expertise (the more the better): Working experience with Complex Embedded Systems, Mobile/ IOT/Auto domains preferred. Expertise in fields such as power performance use cases , system modeling, SOC Profiling, PPA tradeoffs, post silicon bring up, and product qual. Firm grasp of computer architecture and OS fundamentals Post Silicon System Validation of SOC Performance, Architecture Analysis and Feedback to future products. Analyzing the power-performance data for various CPU, GPU, AI workloads benchmarks Conducting detailed workload characterization and sensitivity analysis Develop and enhance analysis tools and instrumentation to assist in analysis, identifying performance gaps and optimization options CPU microarchitecture including cache, Latency, BW analysis, etc. Linux/Android kernel development, device driver development and Android architecture experience Collaborate with the architecture team on power-performance trade-off analysis as part of product definition. Power and/or performance optimization, CPU, SOC SW DCVS/DVFS Governors exposure Working experience at System level, Linux kernel internals system programming Collaborate with internal teams and external partners for analysis and optimizations Lab Hands-on: with Power Data Acquisition/DAQs, Oscilloscope, JTAGs, ARM Developer Studio exposure Exposure to ADB shell, shell scripts, Python scripts, Understanding of Linux/android systems , automation scripts/environment Exposure to Git, Jira, Android and QTI tools Good communication skills, presentation skills and should manage his/her tasks independently Acts as a tech lead on projects and owns the outcome of the project.