4 Power Intent Jobs

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4.0 - 12.0 years

0 Lacs

karnataka

On-site

Role Overview: You have 12+ years of experience in Digital ASIC/Processor Design with strong fundamentals in core areas such as Microarchitecture, Computer Arithmetic, Circuit Design, and Process Technology. Your communication skills are excellent, enabling you to collaborate effectively with design teams globally. Key Responsibilities: - Lead, train, and mentor a team of junior engineers for a large modem design project in advanced process nodes - Collaborate with RTL, DFT, and PD leads to take a project from Post-RTL to Netlist release, focusing on area, timing, power, and testability - Write timing constraints, conduct synthesis, formal verification, CLP, Primetime, PTPX, and CECO tasks -...

Posted 1 month ago

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3.0 - 7.0 years

0 Lacs

karnataka

On-site

As a Synthesis & STA engineer, you will be responsible for performing RTL Synthesis to optimize the Performance/Power/Area of the designs. Your role will involve DFT insertions such as MBIST and SCAN, setting up Timing Constraints for functional and Test Modes, and Validation. You will be expected to create Power Intent for the designs, verify power intent on RTL, run static Low-Power checks on gate level netlists, and ensure Logic Equivalency Checks between RTL to Gates and Gates to Gates. Collaborating with the Design/DFT/PD teams, you will set up signoff Static Timing Analysis and ECO flows to achieve timing closure. Additionally, you will be involved in Power Analysis, estimating power a...

Posted 1 month ago

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1.0 - 12.0 years

0 Lacs

karnataka

On-site

As an engineer at Qualcomm India Private Limited, you will have the opportunity to work on cutting-edge Wireless Technology projects, specifically focusing on IEEE 802.11 standards. Your role will involve collaborating with design teams globally and contributing to the development and implementation of hardware blocks for complex SoCs. You will also play a critical part in the WLAN subsystem, ensuring the successful delivery of IPs to the SOC design team. Strong fundamentals in Microarchitecture, Computer Arithmetic, Circuit Design, and Process Technology will be essential for excelling in this role. Key Responsibilities: - Develop HW blocks (IP design) and conduct High/Mid/Low level Design ...

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5.0 - 9.0 years

0 Lacs

hyderabad, telangana

On-site

In this role at Ambit, you will be responsible for IP / sub-system level micro-architecture development and RTL coding. Your key responsibilities will include: - Prepare block/sub-system level timing constraints - Integrate IP/sub-system - Perform basic verification either in IP Verification environment or FPGA - Deep knowledge of mixed signal concepts - Deep knowledge of RTL design fundamentals - Deep knowledge of Verilog and System-Verilog - Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Power intent, Static Timing Analysis (STA) - Write design specifications for different functional blocks on a chip - Create micro-architecture dia...

Posted 1 month ago

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