8 Power Intent Jobs

Job Description You are a Principal Engineer, Physical Design responsible for leading the implementation and optimization of low-power, chiplet-based MCU designs on cost-optimized mature process nodes. Your primary focus is to deliver high-quality and affordable microcontrollers by utilizing proven technologies and efficient design methodologies. Role Overview: - Own end-to-end physical design for chiplet-based MCU SoCs, which includes floorplanning, placement, power planning, signal integrity, routing, timing closure, and physical verification. - Apply best practices for mature-node design to achieve cost efficiency without compromising performance. - Collaborate with architecture and packa...

Role Overview: Are you ready for a challenging career that also brings a sense of accomplishment At Ambit, you will find the perfect platform to excel and advance in the field of semiconductor design. Enjoy the freedom to work in your unique way while receiving the necessary support to learn and enhance your skills. Ambit believes in fostering innovation by empowering its employees to experiment and create. The vibrant work environment reflects the management's dedication to its people and their values. Join Ambit today for a promising future in semiconductor design services. Key Responsibilities: - Develop micro-architecture at IP/sub-system level and perform RTL coding. - Create timing con...

In this role at Ambit, you will be responsible for IP / sub-system level micro-architecture development and RTL coding. Your key responsibilities will include: - Prepare block/sub-system level timing constraints. - Integrate IP/sub-system. - Perform basic verification either in IP Verification environment or FPGA. - Deep knowledge of mixed signal concepts - Deep knowledge of RTL design fundamentals - Deep knowledge of Verilog and System-Verilog - Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Power intent, Static Timing Analysis (STA) - Write design specifications for different functional blocks on a chip, create micro-architecture d...

As a Digital ASIC / Processor Design Lead at Qualcomm India Private Limited, you will have the opportunity to showcase your expertise in high-speed and low-power 5G and WLAN modem hardmacro implementation. Your responsibilities will include leading, training, and mentoring a team of junior engineers to execute a complex project for a large modem design in advanced process nodes. You will collaborate closely with RTL, DFT, and PD leads worldwide to take a project from Post-RTL to Netlist release, ensuring convergence on area, timing, power, and testability. Your primary tasks will involve writing timing constraints, synthesis, formal verification, CLP, Primetime, PTPX, and CECO. You will be t...

Role Overview: You have 12+ years of experience in Digital ASIC/Processor Design with strong fundamentals in core areas such as Microarchitecture, Computer Arithmetic, Circuit Design, and Process Technology. Your communication skills are excellent, enabling you to collaborate effectively with design teams globally. Key Responsibilities: - Lead, train, and mentor a team of junior engineers for a large modem design project in advanced process nodes - Collaborate with RTL, DFT, and PD leads to take a project from Post-RTL to Netlist release, focusing on area, timing, power, and testability - Write timing constraints, conduct synthesis, formal verification, CLP, Primetime, PTPX, and CECO tasks -...

As a Synthesis & STA engineer, you will be responsible for performing RTL Synthesis to optimize the Performance/Power/Area of the designs. Your role will involve DFT insertions such as MBIST and SCAN, setting up Timing Constraints for functional and Test Modes, and Validation. You will be expected to create Power Intent for the designs, verify power intent on RTL, run static Low-Power checks on gate level netlists, and ensure Logic Equivalency Checks between RTL to Gates and Gates to Gates. Collaborating with the Design/DFT/PD teams, you will set up signoff Static Timing Analysis and ECO flows to achieve timing closure. Additionally, you will be involved in Power Analysis, estimating power a...

As an engineer at Qualcomm India Private Limited, you will have the opportunity to work on cutting-edge Wireless Technology projects, specifically focusing on IEEE 802.11 standards. Your role will involve collaborating with design teams globally and contributing to the development and implementation of hardware blocks for complex SoCs. You will also play a critical part in the WLAN subsystem, ensuring the successful delivery of IPs to the SOC design team. Strong fundamentals in Microarchitecture, Computer Arithmetic, Circuit Design, and Process Technology will be essential for excelling in this role. Key Responsibilities: - Develop HW blocks (IP design) and conduct High/Mid/Low level Design ...

In this role at Ambit, you will be responsible for IP / sub-system level micro-architecture development and RTL coding. Your key responsibilities will include: - Prepare block/sub-system level timing constraints - Integrate IP/sub-system - Perform basic verification either in IP Verification environment or FPGA - Deep knowledge of mixed signal concepts - Deep knowledge of RTL design fundamentals - Deep knowledge of Verilog and System-Verilog - Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Power intent, Static Timing Analysis (STA) - Write design specifications for different functional blocks on a chip - Create micro-architecture dia...