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Senior Principal Design Engineer Cadence Design Systems

10.0 - 15.0 years

3 - 9 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

Minimum Qualifications & Professional Experience: 10-15 years (with BTech) or 10 years (with MTech) experience in Post-Silicon PHY, Systems Interop and Compliance testing. 2-3 years of management experience leading/mentoring a small team of engineers Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on Ethernet/PCIe/CXL/UCIe/ Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers. Proficient with Ethernet, PCIe, UCIe standards and Protocols. Proven experience to interpret the standard s specification to develop Electrical and Protocol, Interoperability and Compliance test suites to validate...

Posted 4 months ago

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