0.0 years

0 Lacs

india

On-site

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. To...

Posted 1 week ago

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DFT Lead Evnek

12.0 - 15.0 years

8 - 12 Lacs

mumbai, delhi / ncr, bengaluru

Work from Office

As a DFT Lead, you will be responsible for defining, developing, and implementing Design-For-Test (DFT) methodologies for high-performance LiDAR SoCs. You will own DFT planning, insertion, verification, and validation, and collaborate with RTL, Physical Design, IP vendors, and ASIC partners to ensure proper DFT implementation. The role includes supporting post-silicon bring-up, silicon debug, yield improvement, and creating/maintaining documentation and DFT guidelines. You will ensure robust test strategies for automotive-grade SoCs with focus on reliability, quality, and compliance. Location-Remote, Delhi NCR, Bangalore, Chennai, Pune, Kolkata, Ahmedabad, Mumbai, Hyderabad

Posted 1 month ago

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DFT Design Engineer -Memory Team Samsung

5.0 - 8.0 years

5 - 8 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

Roles and Responsibilities Good Experience in Top/Block, FLAT/Hier DFT insertion flow methodologies Executed scan & MBIST insertion, ATPG and verification at full chip level Experience in timing closure in DFT modes - understanding of shift, capture timing constraints, MBIST constraints and their impacts Generate, review and validate DFT constraints to achieve timing closure of high speed design Experience in timing closure in DFT modes, RTL analysis, logic synthesis, physical design, signoff verification (STA, Formality, Simulations) Exposure to analog and mixed signal IP tests such as PLLs, MIPI etc., methods of their pattern generation and verification Exposure to post-silicon bring-up. D...

Posted 4 months ago

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R&D Engineering, Sr Engineer Synopsys

1.0 - 5.0 years

3 - 11 Lacs

Bhubaneswar, Odisha, India

On-site

What You ll Be Doing: * Serving as the single point of contact for post-silicon debug activities. * Enabling Product Requirement Documents (PRDs). * Working to enable IP as a product development platform. * Handling hands-on post-silicon test setups. * Collaborating on top-level physical design, board-level, and package-level designs. * Developing post-silicon reports and conducting debug analysis. The Impact You Will Have: * Driving the successful development and deployment of PVT IP sensors. * Enhancing the reliability and performance of Synopsys silicon lifecycle monitoring solutions. * Ensuring high-quality product development through meticulous testing and debugging. * Contributing to t...

Posted 5 months ago

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