8 Pnr Tools Jobs

As a Senior Member of Technical Staff (SMTS) Silicon Design Engineer at AMD, you will be part of a highly experienced CPU physical design team, responsible for delivering the physical design of critical CPU units to meet challenging goals for frequency, power, and other design requirements for AMD's next-generation processors. Your role will be crucial in a fast-paced environment with cutting-edge technology. Key Responsibilities: - Own critical CPU units and drive to convergence from RTL-to-GDSII, including synthesis, floor-planning, place and route, timing closure, and signoff. - Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoff...

Job Title: PD EMIREngineer Location: Banglaore/Hyderabad Employment Type: Full-time Industry: Semiconductors / VLSI / ASIC Design Job Summary: We are looking for a skilled and motivated PD EMIR Engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting performance, power, and area (PPA) optimization and signoff closure. Key Responsibilities: Experience in ASIC EMIR/PD flow and EDA tools experience such as Redhawk-SC , Redhawk IR and EM Analysis tool Analyze EMIR violations and provide implementation choices to Physical design Scripting language experience: Python, perl, shell preferr...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity ...

As a Qualcomm Hardware Engineer, your role involves planning, designing, optimizing, verifying, and testing electronic systems. You will work on a variety of systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. Key Responsibilities: - Utilize your 3 to 5 years of experience in static timing analysis, constraints, and other physical implementation aspects - Demonstrate a solid understanding of industry standard tools such as PT, Tempus, and familia...

As a Hardware Engineer at Qualcomm India Private Limited, you will be responsible for the physical design aspects of ASICs, including Place and Route (PnR) flow and methodology. Your key responsibilities will include: - Executing complete PD ownership from netlist to GDS2, encompassing HM level PV, LEC, low-power checks, PDN, and STA closure - Implementing Voltage Islands and low power methodologies, flows, and implementation - Debugging Congestion and Clock Tree Synthesis (CTS) issues - Utilizing PnR tools such as Innovus/Fusion compiler and flow - Familiarity with Sign-off methodologies and tools (PV/PDN/STA/FV/CLP/Scan-DRC(tk)) - Enhancing existing methodologies and flows - Proficiency in...

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drive digital transformation. As a Qualcomm Hardware Engineer, your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems. You will work on a variety of systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. The ideal candidate for this role should ...

You will be responsible for leading Static Timing Analysis (STA) and Place and Route (PNR) activities for complex subsystems within ASIC/SoC design. Your focus will be on achieving robust timing closure and optimizing physical implementation in terms of power, performance, and area. Your role will involve developing and refining methodologies for STA and PNR specifically tailored to address the challenges posed by large, multi-interface, or mixed-signal subsystems. You will drive automation and validation of timing and physical design data across subsystem boundaries to ensure seamless integration. As a key member of the team, you will mentor and guide junior engineers, fostering their techn...

We are looking for highly skilled Physical Verification Engineers to join our team. The ideal candidates will have extensive experience in physical verification tasks such as DRC, LVS, and parasitic extraction using tools like Mentor Graphics Calibre. You will be working on cutting-edge technologies and collaborating with cross-functional teams to ensure seamless tapeouts and compliance with foundry design rules. Your main responsibilities will include implementing Physical Verification with a focus on hard macro/core finishing activities. You must have led and been primarily responsible for physical verification checks, fixing, and sign-off. It is essential to have an excellent understandin...