4 Pnr Tools Jobs

As a Hardware Engineer at Qualcomm India Private Limited, you will be responsible for the physical design aspects of ASICs, including Place and Route (PnR) flow and methodology. Your key responsibilities will include: - Executing complete PD ownership from netlist to GDS2, encompassing HM level PV, LEC, low-power checks, PDN, and STA closure - Implementing Voltage Islands and low power methodologies, flows, and implementation - Debugging Congestion and Clock Tree Synthesis (CTS) issues - Utilizing PnR tools such as Innovus/Fusion compiler and flow - Familiarity with Sign-off methodologies and tools (PV/PDN/STA/FV/CLP/Scan-DRC(tk)) - Enhancing existing methodologies and flows - Proficiency in scripting languages like TCL, PERL, and PYTHON - Working effectively in a global team environment - Communicating status and issues of owned tasks effectively Qualifications required for this role include: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 4+ years of Hardware Engineering experience, or - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 3+ years of Hardware Engineering experience, or - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 2+ years of Hardware Engineering experience - 4-10 years of experience in physical design, including floorplanning, PNR, CTS, and signoff checks If you are an individual with a disability and need accommodation during the application/hiring process, Qualcomm is committed to providing accessible support. You may contact disability-accommodations@qualcomm.com for assistance. Qualcomm expects all employees to adhere to applicable policies and procedures, including those related to confidentiality and security. Please note that Qualcomm's Careers Site is intended for individuals seeking jobs directly at Qualcomm, and staffing/recruiting agencies are not authorized to submit profiles, applications, or resumes through this platform. If you require more information about this role, please reach out to Qualcomm Careers directly.,

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drive digital transformation. As a Qualcomm Hardware Engineer, your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems. You will work on a variety of systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. The ideal candidate for this role should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field. Additionally, you should have 3 to 5 years of experience in static timing analysis, constraints, and other physical implementation aspects. A solid understanding of industry-standard tools such as PT, Tempus, and familiarity with PNR tools like Innovus/FC is required. Proficiency in fixing STA aspects to solve extreme critical timing and clock path analysis is essential. Experience in preparing complex ECOs for timing convergence across a wide range of corners through Tweaker, Tempus, Physical PT ECOs, and manual ECOs is highly valued. Candidates with experience in deep submicron process technology nodes, particularly below 10nm, are strongly preferred. Knowledge of high-performance and low-power interface timing is considered an added benefit. A strong grasp of basic VLSI design concepts, synchronous design timing checks, and understanding of constraints is necessary. Proficiency in Unix, TCL, PT-TCL, Tempus-TCL scripting is required, with familiarity with Python background being an added bonus. Qualcomm is an equal opportunity employer and is committed to providing reasonable accommodations for individuals with disabilities during the application/hiring process. For accommodation requests, individuals may contact disability-accommodations@qualcomm.com or Qualcomm's toll-free number. The company expects its employees to adhere to all applicable policies and procedures, including those related to security and the protection of confidential information. Qualcomm does not accept unsolicited resumes or applications from staffing and recruiting agencies. For more information about this role, please contact Qualcomm Careers directly.,

You will be responsible for leading Static Timing Analysis (STA) and Place and Route (PNR) activities for complex subsystems within ASIC/SoC design. Your focus will be on achieving robust timing closure and optimizing physical implementation in terms of power, performance, and area. Your role will involve developing and refining methodologies for STA and PNR specifically tailored to address the challenges posed by large, multi-interface, or mixed-signal subsystems. You will drive automation and validation of timing and physical design data across subsystem boundaries to ensure seamless integration. As a key member of the team, you will mentor and guide junior engineers, fostering their technical growth and promoting knowledge sharing within subsystem teams. Collaboration across functions to address design, timing, and physical implementation challenges unique to complex subsystem integration will be a crucial aspect of your responsibilities. Your excellent communication skills will be essential for presenting technical solutions and leading discussions with internal teams and customers, especially in relation to subsystem-level trade-offs and integration. To be successful in this role, you should have at least 10 years of experience in STA and PNR for complex subsystems within ASIC/SoC design, including expertise in advanced technology nodes (7nm or below). Proficiency in tools such as Synopsys PrimeTime, Cadence Tempus for STA, and Synopsys ICC2, Cadence Innovus for PNR applied to large, multi-block, or hierarchical subsystems is required. Experience in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems is essential. Additionally, you should be proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows across multiple subsystem blocks. A deep understanding of SoC design flows and experience collaborating across frontend, physical design, and verification teams to integrate complex subsystems will be advantageous. Background knowledge in high-speed interfaces or mixed-signal SoC subsystems is preferred. Join Renesas to be a part of a global team dedicated to building a sustainable future where technology enhances lives and shapes the world of electronics. Let's shape the future together at Renesas.,

We are looking for highly skilled Physical Verification Engineers to join our team. The ideal candidates will have extensive experience in physical verification tasks such as DRC, LVS, and parasitic extraction using tools like Mentor Graphics Calibre. You will be working on cutting-edge technologies and collaborating with cross-functional teams to ensure seamless tapeouts and compliance with foundry design rules. Your main responsibilities will include implementing Physical Verification with a focus on hard macro/core finishing activities. You must have led and been primarily responsible for physical verification checks, fixing, and sign-off. It is essential to have an excellent understanding of the Physical Verification flow, with experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues primarily using the Calibre tool. Additionally, a deep understanding of ESD, latch-up, etc., is required. You will be responsible for owning and executing Physical Verification activities at the Top/Block level. Collaborating closely with the PD team to address their PV issues and suggest solutions is a key aspect of the role. Working with CAD team to refine existing flows/methodologies and resolve issues is also part of the job scope. Experience in IO, Bump planning, RDL routing Strategy, and developing/implementing timing and logic ECOs are considered advantageous. Knowledge of tools like Innovus/FC for DRC fixing, Python, PERL/TCL scripting, and the ability to plan, work independently, and coordinate with cross-functional teams are essential. Closing sign off DRC based on PNR markers is a plus. The ideal candidate should have experience with physical verification checks such as DRC, LVS, Antenna, ERC, PERC, ESD, etc. Experience with PnR tools like ICC/Innovus and understanding sign-off PDV tools like PDK Concepts, SVRF, Calibre, and ICV is required. A good overall understanding of the Custom IC design flow, layouts, and backend tool flow would be beneficial. Hands-on experience with tools like Innovus/Fusion Compiler, Tech lef is preferable. People management, floorplanning, power planning, and PDN experience are considered a big plus. The ability to script in TCL/PERL and familiarity with physical convergence in PnR tools are also advantageous. In return, we offer a competitive salary, performance-based bonuses, comprehensive benefits package including health insurance, retirement plans, and paid time off. Additionally, you will have opportunities for professional development and career growth in a collaborative and innovative work environment with state-of-the-art facilities.,