260 Pnr Jobs - Page 6

Role: Training: Training new hire batches on pre-process & Process which includes domain, communications, soft skills and travel induction • People Management: Should be able to identify EWS (Early Warning Signals), provide feedback, create coaching environment Key Accountability: • Hiring: Hiring candidates as per client and process requirement on all communication parameters • Training Performance: End to end responsibility of training deliverables like throughput, certification, early production performance, etc. Conduct interventions during process training and nesting. • Detailed daily New Hire training review • Reporting: Ensure all training reports including internal stakeholder and clients should be shared on time accurately • Content Creation: Should be able to conduct TNI (Training Need Identification) and make changes in pre-process training plan accordingly • Knowledge Management: Ensure floor agents go through timely monthly check, floor refreshers, etc. • Stakeholder Management: Should be able to manage internal communication with peers, stakeholders and clients • Coordination: Conduct interventions during process training and nesting • TNI Refreshers: Identify agent strengths to identify areas of improvement and provide concrete work plan for improvement. Create intervention plan basis TNI including SBS, one on one coaching, briefing, classroom sessions, on floor activities Qualifications Knowledge/ Qualification: Under Graduate/ Graduate Special Role Requirement: • Excellent written and verbal communications. Bilingual in English and German • Should be willing to work in 24*7 environment, (5 days) • Should be willing to work in non-weekend offs • Proficiency in MS office • Travel ready Work Experience: • Travel Experience: +3 Years • Training Experience: Should have sound understanding of the training function and should have spent +2years in training department • Corporate travel experience Certification/ Domain Certification (If Applicable): GDS Certifications will be an added advantage.

Founded in 2023,by Industry veterans HQ in California,US We are revolutionizing sustainable AI compute through intuitive software with composable silicon Staff Physical Design Engineer • Job Description o Be part of a diverse team working on the high performance designs. Youll lead the complex multimillion instance subsystems including high-speed blocks i.e. DDR, PCIe, AI Cores • Technical Requirements o 8-12 years of experience in Physical Design o Expert in PnR, sign off convergence including timing, physical and PDN verification o Experience in sub 5nm technology node with high performance designs o Experience in pushing performance by custom PnR techniques o Expert of STA and eco generation PnR steps o Expert in debugging and fixing flow, tool and design related issues independently o Experience in the solving physical integration design challenges o Expertise in industry standard tools like Innovus/ICC2/Fusion compiler/Primetime o Experience in contributing to physical design flows and methodologies o Expertise in automation scrips(TCL/PERL/Python)for various implementation steps o Experience in leading and mentoring a team o Ability to work cross-functionally with various teams • Academic Credentials o Qualification: Bachelors or Masters in Electronics/Electrical Engineering

What You'll Be Doing : - In this position, you will expect to lead all block/chip level PD activities. - PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification. - Work in collaboration with design team for addressing design challenges. - Help team members in debugging tool/design related issues. - Constantly look for improvement in RTL2GDS flow to improve PPA. - Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. - Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets. Minimum Qualifications : - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. What We Need To See : - Strong experience in Physical Design. - Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure. - Expertise on high frequency design methodologies. Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Working experience with tools like ICC2/Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation. - Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred. - Well versed with timing constraints, STA and timing closure. - Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools. - Ability to multi-task and flexibility to work in global environment. - Good communication skills and strong motivation, Strong analytical & Problem solving skills. - Proficiency using Perl, Tcl, Make scripting is preferred. - Widely considered to be one of the technology worlds most desirable employers, offers highly competitive salaries and a comprehensive benefits package. Require candidates with a minimum of 5 years of relevant experience

Dear Candidate We have immediate job openings for Analog layout and design openings Exp : 3-10 years Location : Bangalore NP : less than 45 days Job details : Analog layout exp Skills Required: Analog Layout design and IO design Good to Have: Exposure to Analog layout, EDA tools Thanks Gayathri

Hiring Travel Backend Profile for Gurgaon Location Air Ticketing, Reservation, PNR creation, issuance, Refunds Upto-32k ctc Plus Incentives+medical insurance Any travel GDS-experienced can apply 5 days Working-rotational Shift Gurgaon Location Required Candidate profile 6months travel experience can apply Ug/Grad both can apply Call or whatsap Rajiya - 9354352748

For our client, a travel company, having offices in Delhi & Mumbai, we are looking for professionals - Ticketing. Excellent command over English, pleasing & convincing personality, good to operate on travel ticketing sites & software. Required Candidate profile Experienced in Air ticketing, using software and sites for the same.. comparison between airlines, excellent communication skills. Looking for best routes to save time and money for the clients.

Basic Section No. Of Position 1 Grade ST Level Staff Organisational Industry -- Function -- Skills Skill Admin Transportation Operations Vehicle Tracking Vehicle Maintenance Bill Processing Logistics Consulting General Administration Onboarding RTO Management Road Safety Audits MIS & Analytics Safety WCM-Interwoven Interpersonal Abilities Coordinating Activities Communication Skills Drafting Official Responses Document Drafting Liaison Minimum Qualification Graduate Diploma in Business Management PGD in Business Administration Bachelor"s Of Hospitality Mgt CERTIFICATION No data available About The Role Job Purpose Role Objective To efficiently manage the planning, deployment, and coordination of company-hired transport services while ensuring adherence to road safety and statutory compliance. The role also extends to overseeing plant general administrative services such as event management, pantry services, and office infrastructure support. Key Responsibilities Plan and deploy company-hired vehicles for employee and guest movement, including timely pick-up/drop at railway stations and airports. Coordinate with the Purchase Team for vehicle hiring requirements through approved transporters. Ensure all deployed vehicles comply with road safety norms and statutory regulations (permits, insurance, driver license, etc.). Monitor and schedule regular vehicle maintenance in coordination with the respective transporter to avoid breakdowns or service delays. Maintain a vehicle deployment log and analyze usage patterns for optimization. Verify and scrutinize transporter bills and ensure timely submission to the accounts department for processing payments. Manage event arrangements within the plant premises, including logistics and coordination with vendors. Oversee pantry operations to ensure cleanliness, hygiene, and timely service across all departments. Coordinate procurement and placement of office furniture in consultation with stakeholders. Ensure proper seating arrangements for employees, especially during transfers, onboarding, or departmental relocations. Maintain an updated asset register for administrative utilities and coordinate repairs/replacements as needed.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux "“ Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills 3+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. General Summary PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux "“ Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 12+ years Hardware Engineering experience or related work experience. 12+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3 to 5 years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, And should be familliar to PNR tools like Innovus/FC Solid grip on STA fixing aspects to solve extreme critical timing and clock path analysis Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs and manual ECOs as well. Experience in deep submicron process technology nodes is strongly preferred - Below 10nm Knowledge of high performance and low power interface timing is added benefit. Strong fundamentals on basic VLSI design concepts, synchronous design timing checks, understanding of constraints Good experience with in Unix, TCL, PT-TCL, Tempus-TCL scripting Familiarity with Python background is added bonus

Hiring Travel Backend Profile for Gurgaon Location Air Ticketing, Reservation, PNR creation, issuance, Refunds Any Travel certificate, travel course can apply Fresher with travel course can apply 5 days Working-rotational Shift Gurgaon Location Required Candidate profile Fresher with travel certification can also apply Ug/Grad both can apply Call or whatsap Mahi - 9871856986 Rajiya - 9354352748

• Physical Design of blocks & handle Complex block implementation. • Floorplan optimization for area, Power & Timing. • Block-level PnR & close Design to meet Timing, area & Power constraints. • Implement ECOs to fix timing, noise & EM-IR violations. Required Candidate profile * Exp in RTL Synthesis for PnR using small geometry FinFET. * Strong in Physical Design incl. physically aware Synthesis, floor-planning, PnR * Logic equivalency RTL2Synthesis & Synthesis2APR netlist.

Ienergizer is hiring for Premium Travel Process | VOICE https://chat.whatsapp.com/I6qY77fnxY07o7yRBP9RN1 Job Responsibilities: 1. Resolve customer complaints via Calls 2. Responding promptly to customer inquiries. 3. Ensure customer satisfaction and provide professional support. Job Requirements: Excellent command on spoken English with fluency. Flexibility to work in 24/7 environment UG / Graduate both can apply. strong knowledge of GDS. (Amadeus/ Galileo) 5 days working Attractive salary package whatsApp on the Below mentioned number to Schedule YOUR interview by writing "INTERVIEW ". (9650832496) Need to mention \ " HR Yamini Srivastav" \ on top of the resume. Interview Details: Contact Person: HR Yamini Srivastav Contact Number: 9650832496 Timing : 12PM - 4 PM Address: A-37, GATE NO. 2 ,Sec- 60, Noida Feel free to refer your friends and share the contact number.

Full chip or block-level synthesis using tools Constraints development, STA & timing closure, low power checks Work closely with PD team for floorplan, placement & timing reviews Good understanding of front-end implementation flows ,concepts

ROLE & RESPONSIBILITIES Engineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity, Power grid analysis atc in ASIC PNR Flow Engineer will be responsible for executing the block level place and route assignments from Netlist through GDS flow Should be able to do full chip implementation of complex SoCs (RTL-to-GDSII), but it is not must. To close STA timing across all corners and modes for blocks and should be able to generate ECO independently. Will be responsible to Work with design teams for closing CTS, IO timing, DFT timing. Responsible for digital design automation, flow-automation and regression across RTL-to-GDSII. To ensure successful delivery of his block(s) to customers ESSENTIAL SKILLS & EXPERIENCE Minimum Experience required is 5 Years in Physical Design Strong fundamentals on Physical design including Floorplan, power grid analysis, placement, cts, routing, DRC-LVS closure, timing closure, antenna fixing, signal integrity on 65nm, 45nm, 28nm, 16nm geometry. Sound expertise in Tcl, Perl, Shell scripting. Technically sound & good team player Hands-on experience with Place and Route tools (Synopsys - ICC, Cadence – Innovus / Encounter) is a must. Experience on latest technology (28nm,16nm,7 nm) EDUCATION BACKGROUND B.E./ B.S./ B.Tech/ M.S./ M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering.

Hello, Hiring for Excellent Opportunity for Travel domain in Mumbai (Navi Mumbai) It is mandatory to have Excellent Communication. UG can apply. Excellent Knowledge of GDS/Sabre/Amadeus/Galileo. CTC Upto 6 Lakhs (42800 in-hand per month) Candidates willing to relocate to Mumbai can be considered, but only those who can join in a maximum of 15 Days. Out of Mumbai candidates, may get a Joining Bonus + 10 to 14 Days of Accommodation + 1 Side Travel Ticket from the Company Side. Interested candidates, kindly share your profile with HR Geeta on WhatsApp with below details and CV 8855961728 Position applying for: Travel Consultant Full Name Contact No. Email ID Current co Current Designation Current CTC Notice period Highest Qualification Total years of Exp in GDS/SABRE/Amadeus/Galileo. Are you willing to relocate to Mumbai Are you willing for 24*7 Shift

Hiring for leading MNC GDS / Amadeus with manual ticketing experience Salary upto 50K in hand 2+ year of Travel experience Call or whatsapp cv Bhavya @ 8130330157

Greetings from ATPI Group!!! We are looking for a candidates with good knowledge in reservation, fresh bookings, ticketing, ticket issue/reissue, ticket cancellation, GDS, Amadeus, Galileo, PNR, etc. Position: Travel Consultant/Sr. Travel Consultant Experience: Any Qualification: HSC/Graduation/Post-Graduation Location: Nahur(WFO) Job description: Proficient in all aspects of domestic and international travel includes air, car, hotel and rail. Process all reservations on behalf of client accounts air, land and other ancillary services Includes all reservation elements including seat assignments and special requests Provides advice and consultation to clients for international documentation Follows best practices for booking and issuing tickets Delivers operational requirements and applies appropriate travel policy guidelines according to client specifications Ensures data quality standards are met including reporting elements and traveler profile information. Balance efficiency and effectiveness Works efficiently to provide prompt service and to meet productivity standards Responsible for managing incoming calls and emails within service level expectations Ensures tickets and informational requests are provided in a timely manner Maintains queues and follow-up on client requests Helps team members with overflow work and tasks Maintains rapport and works professionally with suppliers, vendors and third-party companies Takes steps to avoid debit memos and errors Competencies: Excellent communication skills both written and verbal. GDS experience preferably Amadeus. A good knowledge of world geography/ maritime. Self-assertive, Commercial insight and Effective time management. Qualification & Experience Graduate/ UG in any stream. IATA will be an added advantage. At least 1 year travel industry experience. Interested candidates can share their updated resumes on omkar.tamhane@atpi.com asap.

Hi Mirafra Technologies #Hiring #Physical Design Engineers/ Sr. Engineers SKills Mandatory : # PnR, #floorplanning, #Innovus #placement Experience: 3-5+ years Notice Period - 0 to 30 days Location - #Bangalore Interested candidates can email their updated resumes at kajalmehta @mirafra.com || call / Whatsapp : 9898020056 Role & responsibilities Preferred candidate profile Perks and benefits

Physical Design Engineers We are looking for bright Physical Design Engineer with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering High performance design, flows for high performance SoCs in sub-10nm process for mobile space. Job Requirement: 2-5 years hands-on experience of different PnR steps including Floor planning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation and DRC closure. Well versed with high frequency design & advanced tech node implementation In depth understanding of PG-Grid optimization, including identification of high vs low current density paths & layer/via optimization, Adaptive PDN experience. In depth knowledge of custom clock tree including H-tree, SPINE, Multi-point CTS, Clock metrics optimization through tuning of CTS implementation. Well versed with tackling high placement density/congestion bottlenecks. In depth knowledge of PnR tool knobs/recipes for PPA optimization. Experience in automation using Perl/Python and tcl. Good communication skills and ability & desire to work in a cross-site cross-functional team environment. Experience (years) : 3+ Year Education Qualification: BTECH/ MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Microcircuits technology is looking for DFT Engineers to join our dynamic team and embark on a rewarding career journey. Research and draft blueprints, engineering plans, and graphics. Develop test prototypes. Identify solutions to improve production efficiency. Use design software to develop models and drawings of new products. Maintain existing engineering records and designs. Assess all engineering prototypes to determine issues or risks. Estimate cost limits and budgets for new designs. Supervise the manufacturing process of all designs. Coordinate with other engineers, management, and the creative department.

What You'll Be Doing : - In this position, you will expect to lead all block/chip level PD activities. - PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification. - Work in collaboration with design team for addressing design challenges. - Help team members in debugging tool/design related issues. - Constantly look for improvement in RTL2GDS flow to improve PPA. - Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. - Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets. Minimum Qualifications : - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. What We Need To See : - Strong experience in Physical Design. - Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure. - Expertise on high frequency design methodologies. Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Working experience with tools like ICC2/Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation. - Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred. - Well versed with timing constraints, STA and timing closure. - Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools. - Ability to multi-task and flexibility to work in global environment. - Good communication skills and strong motivation, Strong analytical & Problem solving skills. - Proficiency using Perl, Tcl, Make scripting is preferred. - Widely considered to be one of the technology worlds most desirable employers, offers highly competitive salaries and a comprehensive benefits package.

Skills/Experience: Create emulation models from RTL / Netlist. Expertise in mapping designs to Zebu/Palladium/Haps emulation, improving model performance. Knowledge of the Palladium flow and experience in migrating design on Palladium. Good knowledge of runtime and debug skills. Identifying signals and taking wave dumps on palladium platforms and analyse the failures. Exposure to ARM/ARC cores and its architecture Exposure to AMBA bus architectures like AXI/AHB/APB Exposure to bug tracking tools like Jira and version control tools like Github, Bitbucket, GIT Exposure to Flash(NAND) and HDD(Hard disk) like storage technologies. Experience with Palladium like emulation platforms(Veloce or Zebu or Haps) Understanding of JTAG based debuggers Experience (years) : 3 - 12 Years Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness andparasitic optimisations 3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. 4. Participate in building and enhancing layout flow for faster, higher quality design process. 5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks 6. Collaborate with Circuit Designers to solve challenging problems 7. Writing SKILL/PYTHON scripts to automate repetitive tasks 8. Work with Place and Route engineer to integrate custom macros into top level. 9. Able to perform design reviews across global team 10. Work closely with required global teams to ensure the success of the whole product. 11. Leadership in delivery of macros we plan to own from India Job requirements: 1. Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers etc. 2. Experience in designing layouts for high-speed circuits is a plus. 3. Layout experience in the following technology nodes3nm, 5nm and 7nm FinFET. 4. Good team worker with multi-discipline, multi-cultural and multi-site environments 5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms 6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions 7. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise The Analog layout design engineer with experience in next generation Ultra high speed serial IO link (HSS) interface for Cognitive, ML,DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high speed 32G/50G/112G IO link interfaces. Preferred technical and professional experience Experience in 7 and 14 nm analog layout design. Working on Cutting edge technology and HSS domain . Quick learner, deep layout design knowledge, problem solving skills and good communication skills with cross teams across the Geos.