Principal Engineer, Physical Design Timing Intel Corporation

10.0 - 12.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Responsibilities In this role, you will be responsible for Timing methodology definition and closure of designs using industry standard tools for chiplet designs for custom and domain specific products. The chiplets will be leveraged to enable modular design and support multiple products. As part of this team, the candidate will work with leading edge technologies and solutions across multiple domains including SoC multi-die implementations (2.5 and 3D), power delivery, leading edge memory technologies, innovate thermal solutions, on die clocking, and fabrics. The team will also look at options to enhance product power/performance/area/cost thru improved tools and methodologies. The successf...

Posted 1 month ago

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Application Engineer- Prototyping Siemens EDA (Siemens Digital Industries Software)

3.0 - 7.0 years

0 Lacs

karnataka

On-site

Siemens EDA is a global technology leader in Electronic Design Automation software, enabling companies worldwide to develop innovative electronic products efficiently. Customers utilize Siemens EDA's tools to drive technological advancements in chip, board, and system design within a complex landscape. Based in Bengaluru, this role offers opportunities to travel to various locations in India and globally, providing exposure to diverse projects that impact cities, countries, and future innovations. As part of the team, your responsibilities include deploying Siemens EDA ProFPGA prototyping software and hardware solutions at customer sites, ensuring successful design implementation. Collaborat...

Posted 3 months ago

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UPF & LP check ALOIS Solutions

3.0 - 7.0 years

0 Lacs

karnataka

On-site

You should have a strong understanding of design power intent at the RTL level and UPF. You should be able to translate power intent into UPF after consulting with the RTL designers. Your responsibilities will include running, debugging, and resolving Static Power Check (VCLP) related issues independently before RTL is handed off to PD. Your tasks will involve UPF generation (yaml creation, running upfgen to create the UPF) and UPF maintenance. As RTL changes, UPF may need adjustments and re-verification. You should also be proficient in running VCLP and integrating it with the top level as well as with the P&R flows. We are looking for a UPF expert with a strong background in low power desi...

Posted 3 months ago

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