6 Pnr Flows Jobs

As a CAD Engineer at our company, you will play a critical role in shaping the next generation AMD products, the leader in CPUs, GPUs, and adaptive compute engines. You will be required to interface with large design teams globally and take ownership of developing and supporting next-generation synthesis, place, and route flows. Your responsibilities will include automating PnR flows and methodologies for the 5nm and 3nm technology nodes, as well as collaborating with EDA vendors to identify innovative solutions and track methodology issues. Key Responsibilities: - Develop Place and Route flows for various designs at advanced technology nodes - Script out utilities to automate different comp...

Director- Physical Design About Semifive Founded in Seoul in 2019, SEMIFIVE is basing its foundation on Korea's semiconductor design competency that was amassed for more than 20 years. With expertise spanning front-end to back-end design, SEMIFIVE has become the fastest growing silicon design company that offers the most comprehensive design solutions. SEMIFIVE's core business is its innovative SoC Platform that enables low-cost and high-efficiency SoC design, and also provides full turnkey design services for global customers through its diverse network. As the cost of developing an SoC and the demand for customized silicon continue to grow rapidly, SEMIFIVE's SoC Platform will play a key r...

As a CAD Engineer at AMD, you will play a crucial role in shaping the next generation of AMD products, known for their leadership in GPU and CPU technologies. Your responsibilities will involve interfacing with global design teams, developing and supporting next-generation synthesis, place, and route flows. Your focus will be on automating PnR flows and methodologies for 3nm & 2nm technology nodes, collaborating with EDA vendors for innovative solutions and issue tracking. **Key Responsibilities:** - Develop Place and Route methodologies for various designs at advanced technology nodes - Script utilities to automate different parts of the implementation flow - Provide support to design teams...

Responsibilities In this role, you will be responsible for Timing methodology definition and closure of designs using industry standard tools for chiplet designs for custom and domain specific products. The chiplets will be leveraged to enable modular design and support multiple products. As part of this team, the candidate will work with leading edge technologies and solutions across multiple domains including SoC multi-die implementations (2.5 and 3D), power delivery, leading edge memory technologies, innovate thermal solutions, on die clocking, and fabrics. The team will also look at options to enhance product power/performance/area/cost thru improved tools and methodologies. The successf...

Siemens EDA is a global technology leader in Electronic Design Automation software, enabling companies worldwide to develop innovative electronic products efficiently. Customers utilize Siemens EDA's tools to drive technological advancements in chip, board, and system design within a complex landscape. Based in Bengaluru, this role offers opportunities to travel to various locations in India and globally, providing exposure to diverse projects that impact cities, countries, and future innovations. As part of the team, your responsibilities include deploying Siemens EDA ProFPGA prototyping software and hardware solutions at customer sites, ensuring successful design implementation. Collaborat...

You should have a strong understanding of design power intent at the RTL level and UPF. You should be able to translate power intent into UPF after consulting with the RTL designers. Your responsibilities will include running, debugging, and resolving Static Power Check (VCLP) related issues independently before RTL is handed off to PD. Your tasks will involve UPF generation (yaml creation, running upfgen to create the UPF) and UPF maintenance. As RTL changes, UPF may need adjustments and re-verification. You should also be proficient in running VCLP and integrating it with the top level as well as with the P&R flows. We are looking for a UPF expert with a strong background in low power desi...