Principal Engineer - HBM_SOC Physical Verification Micron

10.0 - 15.0 years

0 Lacs

karnataka

On-site

As an ASIC Physical Verification Engineer at Micron Technology, you will play a crucial role in achieving the best Power, Performance, and Area (PPA) by ensuring the closure of Block/Chip Tile PV. Your responsibilities will involve DRC & LVS closure for both Block and Full Chip designs in complex hierarchical structures at 5nm/3nm nodes. You will have the opportunity to collaborate with various teams such as IR, IP, ESD, and PD to ensure Physical Verification Convergence and resolve conflicts effectively. Additionally, you will be expected to handle multiple blocks simultaneously with minimal supervision, ensuring Full Chip LVS & DRC closure and Analog integration closure for all IPs used in...

Posted 3 weeks ago

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Analog Layout Engineer Digicomm Semiconductor

2.0 - 8.0 years

0 Lacs

karnataka

On-site

You have the opportunity to work as an Analog / Mixed Signal Layout Designer with 2-8 years of hands-on experience in advanced FinFET processes such as 16nm, 12nm, 10nm, 7nm, 5nm, 3nm. Your responsibilities will include: - Expertise in complete PNR flow including CTS, routing, and Timing Closure. - Hands-on experience in critical blocks like SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier, etc. - Understanding of CMOS / Bi-CMOS / SOI / FinFET process and AMS IP integration according to Full Chip needs. - Problem-solving skills in Routing Congestion, Physical Verification in Custom Layout, and verification checks...

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Design Engineer II Cadence

3.0 - 6.0 years

0 Lacs

hyderabad, telangana, india

On-site

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Experience : 3 to 6 + Years Qualification : BE or B.Tech / ME or M.Tech Responsibilities Chip Level IO Planning, Bump Planning and RDL Routing Coordination with FCFP and Block Owners for the RDL integration IP Integration activities for PLL, PVT Sensors etc Required Skills 3+ years of experience in IO & RDL Handson experience in IP DRC and LVS checks and IP Integrations Good in debugging the LVS issues related to IO Plan Good understanding of Latch up issues, soft checks etc. Understanding of PnR flow Good exposure to Cadence EDA or any other tool set needed for IO & RDL Optional Ski...

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Principal Engineer - HBM_SOC Physical Verification Micron

10.0 - 15.0 years

0 Lacs

karnataka

On-site

Role Overview: As a part of Micron Technology, you will play a crucial role in innovating memory and storage solutions, accelerating the transformation of information into intelligence. Your expertise in ASIC Physical Verification and overall design flow will be instrumental in achieving the best PPA for block/chip PV closure and ensuring DRC & LVS closure for complex hierarchical designs. Key Responsibilities: - Achieve block/chip PV closure to optimize PPA - Conduct DRC & LVS closure for block and full chip designs in 5nm/3nm nodes - Collaborate with IR, IP, ESD, and PD teams to ensure Physical Verification convergence - Work on multiple blocks simultaneously with minimal supervision - Ens...

Posted 3 months ago

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