3.0 - 6.0 years

0 Lacs

hyderabad, telangana, india

On-site

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Experience : 3 to 6 + Years Qualification : BE or B.Tech / ME or M.Tech Responsibilities Chip Level IO Planning, Bump Planning and RDL Routing Coordination with FCFP and Block Owners for the RDL integration IP Integration activities for PLL, PVT Sensors etc Required Skills 3+ years of experience in IO & RDL Handson experience in IP DRC and LVS checks and IP Integrations Good in debugging the LVS issues related to IO Plan Good understanding of Latch up issues, soft checks etc. Understanding of PnR flow Good exposure to Cadence EDA or any other tool set needed for IO & RDL Optional Ski...

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Principal Engineer - HBM_SOC Physical Verification Micron

10.0 - 15.0 years

0 Lacs

karnataka

On-site

Role Overview: As a part of Micron Technology, you will play a crucial role in innovating memory and storage solutions, accelerating the transformation of information into intelligence. Your expertise in ASIC Physical Verification and overall design flow will be instrumental in achieving the best PPA for block/chip PV closure and ensuring DRC & LVS closure for complex hierarchical designs. Key Responsibilities: - Achieve block/chip PV closure to optimize PPA - Conduct DRC & LVS closure for block and full chip designs in 5nm/3nm nodes - Collaborate with IR, IP, ESD, and PD teams to ensure Physical Verification convergence - Work on multiple blocks simultaneously with minimal supervision - Ens...

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