Name: Jobpe
Address: T-Hub, Plot No 1/C, Sy No 83/1, Raidurgam panmaktha, Knowledge City Rd, Hyderabad, Telangana, 500081, IN
Telephone: +91-83339-09630
Price range: Free

Mixed Signal Design Engineer JOBWORLD INDIA PRIVATE LIMITED

7.0 - 11.0 years

0 Lacs

hyderabad, telangana

On-site

You are urgently hiring for the position of Analog Mixed Signal Design-Staff Engineer based in Hyderabad. With 7-10 years of experience, you will be responsible for various aspects of Analog and Mixed Signal Design, focusing on PMIC blocks like DC-DC converter (BUCK, BOOST), LDOs, and clocking circuits. Your role will involve circuit design, validation, mixed signal validation, and reliability validation. As an Analog Mixed Signal Design-Staff Engineer, you are expected to possess a strong understanding of CMOS design, active filter design, passive RC circuits, and switched cap circuits. You will work on high-speed digital circuit design and analysis, ensuring timing and flow closure. Additionally, you will utilize digitally assisted analog circuit and techniques to develop high-speed, low-power, and reliable analog and digital circuits for various areas of PLL. Your responsibilities will span across the design and development of cutting-edge foundry process development nodes. It is essential to have good knowledge of control systems, Bandgap reference, bias, op-amps, feedback, compensation techniques, and experience in LC VCO/DCO design. You will also gain exposure to the performance parameters of VCO and complete PLL architecture.,

Posted 1 week ago

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Analog Mixed Signal Design-Staff Engineer Cyient

5.0 - 9.0 years

0 Lacs

hyderabad, telangana

On-site

The ideal candidate should possess experience in Analog and Mixed Signal Design, focusing on PMIC blocks such as DC-DC converter (BUCK, BOOST), LDOs, and clocking circuits. A strong foundation in CMOS design and active filter design is essential for this role. Responsibilities will include circuit design, validation, mixed signal validation, and reliability validation. Exposure to PMIC designs, high-speed digital circuit design, and analysis with timing and flow closure is required. Additionally, knowledge of digitally assisted analog circuits and techniques is preferred. The candidate will be entrusted with developing high-speed, low-power, and reliable analog and digital circuits for various PLL areas. Proficiency in control systems, Bandgap reference, bias, op-amps, feedback, and compensation techniques is necessary. Joining an expanding analog/mixed-signal circuit design team involved in cutting-edge foundry process development nodes, the selected candidate will be expected to focus on Analog blocks and clocking circuits. Proficiency in CMOS design, passive RC circuits, and switched-cap circuits is crucial for success in this role. Task responsibilities will encompass circuit design, validation, mixed signal validation, and reliability validation. Additionally, the candidate should be adept in high-speed digital circuit design and analysis with timing and flow closure, as well as digitally assisted analog circuit and techniques. The role will involve the development of high-speed, low-power, and reliable analog and digital circuits for various PLL areas, requiring a good understanding of control systems, band gaps, bias, op-amps, LDOs, feedback, compensation techniques, as well as experience in LC VCO/DCO design. Exposure to VCO performance parameters and complete PLL architecture is highly desirable.,

Posted 1 month ago

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Ams Layout Design Engineer SOP Technology Services

5.0 - 10.0 years

25 - 40 Lacs

Pune, Ahmedabad, Chennai

Work from Office

Job Title: AMS Layout Design Engineer Job Description 90/130/150nm and higher node with PMIC layout experience. Performs layout and takes corrective actions in such a way that the final result meets all requirements as stated in the Design document, section layout, including all remarks from review, the customer and back annotation. Performs layout in such a way that the final result meets all general layout guidelines and matches 1-to-1 with parameter devices and hierarchy used in simulations. Create floorplan Performs DRC and takes corrective actions if needed until DRC is error free Performs LVS and takes corrective actions if needed until result is successful Performs layout in such a way that final result meets the foundry layout rules. Provides extracted netlist for back annotation to DE as specified in the Design document, section layout. Translates sub block schematics to sub block layouts, taking care of the same hierarchical build-up and respecting the guidelines of the Block review document, section layout. Adds extra useful information to the Block review document, section layout.

Posted 1 month ago

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