Senior Staff Analog Design Samsung Electronics

5.0 - 12.0 years

0 Lacs

karnataka

On-site

As a Senior Analog Designer with 5-12 years of relevant experience in Analog and Mixed Signal Design, you will be responsible for the following: - Designing Low Jitter and high frequency PLLs, including experience with both LC and Ring based PLLs - Handling General Purpose ADC and thermal Sensors IP design - Working on High-speed Serdes Design - Designing LDO, BGR, and other power management blocks The ideal candidate for this role should be prepared for challenging design experiences and exposure to silicon validation. You will have the opportunity to gain full exposure to the IP design cycle in advanced Samsung foundry processes at 4nm and below. Qualifications required for this position i...

Posted 2 weeks ago

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Analog Mixed Signal IC Designer Faststream Technologies

4.0 - 10.0 years

0 Lacs

karnataka

On-site

As an Analog Mixed Signal IC Designer with 4-10 years of experience in Bangalore, you will be responsible for designing, implementing, and verifying analog/mixed-signal IC designs for various motion sensor products. Your role will involve mentoring junior engineers in all areas of product design and evaluating system-level trade-offs for next-generation sensor interfaces. Collaborating with the MEMS design team, you will identify IC architectures to meet performance requirements. Additionally, you will interface with digital design engineers to define and optimize sensor architectures and digital signal processing circuits. Providing guidance to layout engineers on physical design and review...

Posted 3 months ago

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Senior Staff Analog Design Samsung Electronics

5.0 - 12.0 years

0 Lacs

karnataka

On-site

As a Senior Analog designer with 5-12 years of relevant experience in Analog and Mixed Signal Design, you will be responsible for Full IP design in one of the following domains: - Low Jitter and high-frequency PLL Design, including experience in both LC and Ring-based PLL design. - General Purpose ADC and thermal Sensors IP design. - High-speed Serdes Design. - Design of LDO, BGR, and other Power management blocks. The ideal candidate should be prepared for challenging design experiences and exposure to silicon validation. You will have the opportunity to work on the full IP design cycle in the advanced Samsung foundry process, specifically focusing on 4nm and below technologies. To be consi...

Posted 3 months ago

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Senior Staff Analog Design Samsung

5.0 - 12.0 years

5 - 12 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

Position Summary Senior Analog Designer with relevant experience of 512 years in Analog and Mixed-Signal Design. Must have full IP design experience in at least one of the domains listed below. Roles and Responsibilities Low-jitter and high-frequency PLL design experience, including both LC and ring-based PLLs General-purpose ADC and thermal sensor IP design experience High-speed SerDes design experience LDO, BGR, and other power management block design Ideal candidate should be ready for challenging design assignments and exposure to silicon validation Opportunity to gain full exposure to the IP design cycle in advanced Samsung Foundry processes (4nm and below) Skills and Qualifications B.T...

Posted 4 months ago

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Analog design, Principal Engineer Synopsys

6.0 - 12.0 years

6 - 12 Lacs

Noida, Uttar Pradesh, India

On-site

You're an experienced and passionate Analog and Mixed-Signal (A&MS) Senior Circuit Design Expert with a strong background in PLL and SERDES design . You bring a deep understanding of mixed-signal techniques for dynamic and static power reduction, performance enhancement, and area reduction. Your expertise covers circuit architectures simulation, circuit layout, and knowledge of bipolar, CMOS, passive structures, and interconnect failure modes in advanced FinFET technology nodes. You excel at developing Analog Full Custom circuit macros , including PLLs, Clock Path Functions, clocking solutions, TX/RX datapaths, and power management and regulation for High Speed PHY IP in both planar and FinF...

Posted 5 months ago

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