4 Pll Design Jobs

As an Analog Mixed Signal IC Designer with 4-10 years of experience in Bangalore, you will be responsible for designing, implementing, and verifying analog/mixed-signal IC designs for various motion sensor products. Your role will involve mentoring junior engineers in all areas of product design and evaluating system-level trade-offs for next-generation sensor interfaces. Collaborating with the MEMS design team, you will identify IC architectures to meet performance requirements. Additionally, you will interface with digital design engineers to define and optimize sensor architectures and digital signal processing circuits. Providing guidance to layout engineers on physical design and reviewing layouts for optimal design will be part of your responsibilities. Ensuring timely tape-out of designs adhering to required specifications is crucial. You will evaluate and validate designs in the lab, identify any deviations from requirements, and implement corrective actions. Performing any other duties or tasks assigned from time to time is also expected. The ideal candidate should hold a minimum of a Bachelors/Masters in EE with at least 4 years of industry experience in analog or mixed-signal CMOS circuit design. You should have a thorough understanding of analog and mixed-signal systems, micro-architecture trade-offs, and the ability to develop micro-architectures and high-level Matlab system models. A proven track record in designing low-power, low-noise, precision CMOS analog circuits for high-volume manufacturing is essential. Strong skills in designing various analog/mixed-signal blocks such as MEMS sense amplifiers, Bandgap References, Regulators, Charge pumps, ADCs, Oscillator circuits, and PLLs are required. Experience as an IC lead on at least one project with demonstrated success is preferred. Knowledge of design for test approaches and the development of characterization and production test plans is beneficial. Proficiency in lab and test equipment skills for the debug, characterization, and validation of designs is expected. Being diligent, detail-oriented, and proactive in process and flow improvements are qualities that will contribute to your success in this role. Your responsibilities will also involve developing DACs, Headphone, Line, and Speaker drivers, Proprietary Low-Voltage Line Drivers, DC/DC Converters, and various supporting circuitry in advanced CMOS processes. You will participate in all aspects of the design, from concept to production silicon. Involvement in the specification, architectural development, transistor-level design, SPICE, Matlab, and Verilog modeling and simulation, layout supervision, post-layout simulation, chip-level verification, and lab validation is part of the job. Specifically, you will develop PLL and low-jitter filters and gain hands-on experience with Audio CODEC applications and circuits across different CMOS processes and geometry nodes.,

As a Senior Analog designer with 5-12 years of relevant experience in Analog and Mixed Signal Design, you will be responsible for Full IP design in one of the following domains: - Low Jitter and high-frequency PLL Design, including experience in both LC and Ring-based PLL design. - General Purpose ADC and thermal Sensors IP design. - High-speed Serdes Design. - Design of LDO, BGR, and other Power management blocks. The ideal candidate should be prepared for challenging design experiences and exposure to silicon validation. You will have the opportunity to work on the full IP design cycle in the advanced Samsung foundry process, specifically focusing on 4nm and below technologies. To be considered for this role, you should hold a B.Tech/M.Tech/PhD degree with expertise in Analog and Mixed Signal Design.,

Position Summary Senior Analog Designer with relevant experience of 512 years in Analog and Mixed-Signal Design. Must have full IP design experience in at least one of the domains listed below. Roles and Responsibilities Low-jitter and high-frequency PLL design experience, including both LC and ring-based PLLs General-purpose ADC and thermal sensor IP design experience High-speed SerDes design experience LDO, BGR, and other power management block design Ideal candidate should be ready for challenging design assignments and exposure to silicon validation Opportunity to gain full exposure to the IP design cycle in advanced Samsung Foundry processes (4nm and below) Skills and Qualifications B.Tech / M.Tech / Ph.D. in relevant fields

You're an experienced and passionate Analog and Mixed-Signal (A&MS) Senior Circuit Design Expert with a strong background in PLL and SERDES design . You bring a deep understanding of mixed-signal techniques for dynamic and static power reduction, performance enhancement, and area reduction. Your expertise covers circuit architectures simulation, circuit layout, and knowledge of bipolar, CMOS, passive structures, and interconnect failure modes in advanced FinFET technology nodes. You excel at developing Analog Full Custom circuit macros , including PLLs, Clock Path Functions, clocking solutions, TX/RX datapaths, and power management and regulation for High Speed PHY IP in both planar and FinFET CMOS technology. You thrive in collaborative environments, working closely with silicon test and debug experts to enhance quality through Sim2Sil correlation . You're also passionate about building and nurturing analog design talent to boost business impact through successful project execution. What You'll Be Doing: Leading SERDES analog design and development. Analyzing various mixed-signal techniques for power reduction, performance enhancement, and area reduction. Developing Analog Full Custom circuit macros for High Speed PHY IP in advanced technology nodes. Collaborating with silicon test and debug experts for Sim2Sil correlation. Building and nurturing a team of analog design talent. Working with experienced teams both locally and globally. The Impact You Will Have: Driving innovation in mixed-signal analog design. Enhancing the performance and efficiency of high-speed physical interfaces. Contributing to the development of cutting-edge technology in High Speed PHY IP. Improving quality and reliability through collaboration and Sim2Sil correlation. Growing the business impact by building and leading a talented team. Advancing Synopsys leadership in chip design and IP integration. What You'll Need: BE with 18+ years or MTech with 15+ years of relevant experience in mixed-signal analog, clock, and datapath circuit design. Strong knowledge of RF architecture and blocks such as transceivers, VCOs, LNA, and up/down converters. Experience in designing Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits. Proficiency in high-speed digital circuit design and timing/phase noise analysis. Ability to create behavioral models of PLL to drive architectural decisions. Who You Are: Possessing strong fundamentals in CMOS, device physics, and sub-micron design methodologies. Experienced with PLL designs and high-speed digital circuit design. Knowledgeable in control systems, band gaps, bias, op-amps, LDOs, and feedback techniques. Experienced in LC VCO/DCO design and performance parameters of VCO. Familiar with digitally assisted analog circuit techniques. The Team You'll Be A Part Of: You'll be joining an expanding analog/mixed-signal SERDES team focused on the design and development of cutting-edge High Speed Physical Interface Development . You'll collaborate with experienced teams locally and with colleagues from various sites across the globe, fostering a truly collaborative and innovative environment.