1 Placement Optimizations Jobs

Name: Jobpe
Address: T-Hub, Plot No 1/C, Sy No 83/1, Raidurgam panmaktha, Knowledge City Rd, Hyderabad, Telangana, 500081, IN
Telephone: +91-83339-09630
Price range: Free

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Associate II - VLSI-Physical Design UST Global

4.0 - 8.0 years

0 Lacs

karnataka

On-site

As a Physical Design Engineer at UST, you will be responsible for the following: - Expected to be very good in Basic Fundamentals of C-MOS technology - Able to handle RTL/Netlist to GDSII independently at block level and should have done multiple tape outs (Low power implementation is preferred) - Hands-on experience of working on Lower technology nodes like 5nm, 7nm, 10nm, 14nm, 16nm, 28nm etc. - Proficient in floor planning, placement optimizations, clock tree synthesis (CTS), and routing - Experienced in block/top level signoff Static Timing Analysis (STA), physical verification (DRC/LVS/ERC/antenna) checks, and other reliability checks (IR/EM/Xtalk) - Expertise in industry standard EDA t...

Posted 2 weeks ago

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