357 Placement Jobs - Page 4

Screening, sourcing candidates from portals, references and Hunting talent for our Pan India-based clients Scheduling interviews, follow up for interviews and post-selection joining Coordinating end-to-end recruitment for Mid and senior-level posts Required Candidate profile Must have recruitment or Consulting background Target oriented, self driven, team player Good communication skills and good system work knowledge Customer and client interaction may require

Screening, sourcing candidates from portals, references and Hunting talent for our Pan India-based clients Scheduling interviews, follow up for interviews and post-selection joining Coordinating end-to-end recruitment for Mid and senior-level posts Required Candidate profile Must have recruitment or Consulting background Target oriented, self driven, team player Good communication skills and good system work knowledge Customer and client interaction may require

Screening, sourcing candidates from portals, references and Hunting talent for our Pan India-based clients Scheduling interviews, follow up for interviews and post-selection joining Coordinating end-to-end recruitment for Mid and senior-level posts Required Candidate profile Must have recruitment or Consulting background Target oriented, self driven, team player Good communication skills and good system work knowledge Customer and client interaction may require

Screening, sourcing candidates from portals, references and Hunting talent for our Pan India-based clients Scheduling interviews, follow up for interviews and post-selection joining Coordinating end-to-end recruitment for Mid and senior-level posts Required Candidate profile Must have recruitment or Consulting background Target oriented, self driven, team player Good communication skills and good system work knowledge Customer and client interaction may require

Screening, sourcing candidates from portals, references and Hunting talent for our Pan India-based clients Scheduling interviews, follow up for interviews and post-selection joining Coordinating end-to-end recruitment for Mid and senior-level posts Required Candidate profile Must have recruitment or Consulting background Target oriented, self driven, team player Good communication skills and good system work knowledge Customer and client interaction may require

Urgent Hiring for Female HR Recruiter for Karelibuag Area. Requirement:- Good communication skills. Graduate Fresher/Exp can apply. Female can apply only. Should be from nearby location. Salary 10000- 12000 (Depends on Exp.)

Experienced Candidate to lead our Placement division.Candidate need have a network within multiple industry and a track record of facilitating placements.The role involves P&L, Achieving revenue target. Proven experience of handling Placement company

Placement Officer MBA Graduate from Pune Area with 3 to 4 years of relevant experience with good communication skills Generate employment opportunities for IT students for software application development. To obtain employment and experiential opportunities in business and industry for students in all curricula. Counsel, prepare, and enhance the hiring potential of students, and new graduates into the job market. Should be energetic, willing to travel, and ready to research on companies in the IT Domain that are likely to hire resources for Big Data, Security, Networking,AI, Application Development, Mobile Development, etc.

SKS Enterpprises is looking for Manager/ Sr Manager - Placement to join our dynamic team and embark on a rewarding career journey Career Counseling: Provide guidance and career counseling to students or job seekers, helping them identify their skills, interests, and career goals Job Placement: Facilitate job placements by matching candidates with suitable job openings based on their qualifications and preferences Employer Engagement: Build and maintain relationships with employers, businesses, and organizations to understand their hiring needs and requirements Job Postings and Recruitment: Post job vacancies and coordinate recruitment processes, including conducting interviews and coordinating selection procedures Resume and Interview Preparation: Assist candidates in preparing resumes, cover letters, and interview techniques to enhance their chances of securing a job Internship and Training Opportunities: Identify and promote internship and training opportunities for students and job seekers to gain practical experience Networking Events: Organize job fairs, networking events, and industry-specific workshops to connect candidates with potential employers

Organization: THE CAREER COACH Need Freshers with EXCELLENT ENGLISH COMMUNICATION skills. Profile : End to end recruitment. Sourcing, Screening profiles. Experience: 0-1yr Salary: Best in the industry Location: South Kolkata Call : 7003500412 Perks and benefits Best in the industry

Job Title : Placement Executive Location : Parul University, Vadodara, Gujarat Reports to : Registrar Job Summary : Parul University seeks a motivated Placement Executive to manage training and placement activities, build industry connections, and create career opportunities for students across diverse fields. The role involves coordinating recruitment drives, organizing training programs, and fostering partnerships with companies to enhance student employability. Key Responsibilities : Build and maintain relationships with recruiters and industries. Organize campus recruitment drives, job fairs, and internships. Conduct pre-placement training, including resume building and interview preparation. Manage placement data and generate reports on recruitment outcomes. Plan seminars, guest lectures, and industry visits for student exposure. Qualifications : Graduate/Postgraduate degree in a relevant field. 2-3 years of experience in placements, recruitment, or a related role. Strong communication, networking, and organizational skills. Willingness to commit to a 3-year tenure. Walk-In Interview: Date: 8th December 2024, Sunday Reporting Time: 10:00 AM Location: HR Department C, Admin Block, Parul University, Vadodara, Gujarat How to Apply : Send your resume to hr@paruluniversity.ac.in within 5 days of this advertisement. Website : www.paruluniversity.ac.in Contact : +91-70583 30296

Job title: Sr. Training & Placement Manager Job Description: Visit industries and companies within the city to explore placement opportunities for students. Build and maintain strong industry connection to foster collaborative opportunities. Strategize and execute initiatives to enhance industry-academia relationships. Job Locations: Mumbai / Kolkata Interested candidates can send their applications along with latest updated resume on gaurav.bharadwaj36358@paruluniversity.ac.in. Application open till 7 days from the date of Job Advertisement Posting.

Lead training & placements, build top recruiter ties, boost student career success. Strategic thinker with industry links. Salary up to 40 LPA.

Rostering of Faculty, Batch Formation, Monthly Faculty Meet, Course ware distribution, Student Grooming Check Maintain Good Relations with Airlines, Hotels & Travel Agency Ensure smooth placement drives, create new clients SIPS 9793664477 Required Candidate profile Female ageing 25-35 with 4-8 Yrs. exp in a similar position in a Training Institute Local Travel required Pleasing personality & excellent communication skills

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Job Responsibilities: Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 2+ years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Minimum 3+ years of experience in PD Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience

Candidate should have good communication and convincing skills. Ready to handle the team and as well as hot and cold calls. Incentive Per candidate wise upto 7.5K. Candidate should be more confident and achieve the target. Salary Negotiable.

SUMMARY Field sales opening in Pune / Nagpur / Aurangabad / Nashik region in a leading MNC. Location: Pune / Nagpur / Aurangabad / Nashik Salary: 13500 to 15000 + upto 6k Incentives Shift time: Day shift (9.30 / 10 am to 7 to 7.30pm) Job details: -Visit minimum assigned outlets daily following a pre-determined route plan to maximize coverage. -Develop and maintain a thorough understanding of our product portfolio to communicate features effectively, benefits, and value to retailers. - Proactively engage with retailers to secure sales orders for our products, ensuring accurate order placement and fulfilment - Merchandising within each outlet to enhance product visibility, including warm and chilled display, and point-of-sale material placement. - Build and maintain strong relationships with retail partners to foster collaboration and ensure ongoing sales growth. - Accurately track and report daily sales activities, including outlet visits, orders generated, and merchandising efforts - Gather feedback from retailers regarding product performance, market trends, and competitive activities. - Ensure 6 days x 8 hours of market work in a week excluding holidays as per company norms - Visit minimum 50 assigned outlets daily following a pre-determined route plan to maximize coverage - Minimum 50% Productivity against the daily visited outlets - Achieve 175 physical cases of daily volume Requirements Work Type: Field Sales Business development executive Qualification: Any Undergraduate/Graduate fresher and experience both can apply 6 days working, 1 rotational week off Benefits - Incentive upto 6k - Day shift

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Job Responsibilities: Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 2+ years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Minimum 3+ years of experience in PD Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Job Responsibilities: Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 2+ years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Minimum 3+ years of experience in PD Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience

Inform students regarding the interview schedule Coordinate with students and companies and align interviews Assist students in all aspects of the job search including resume writing, interviewing techniques, job openings Visit to corporate office

You need to manage end-to-end student placement. coordinating with hiring partners, shortlisting candidates, scheduling interviews, and ensuring successful onboarding. Maintain student placement records, and support career readiness through training.

Job Title: Lead RTL to GDS Engineer Block/Sub-System Level Company: Wafer Space an ACL Digital Group Location: Bangalore, India Experience: 7+ - 20+ Years Notice Period: Immediate to 30 Days Compensation: Best in Industry Overview: Wafer Space, part of ACL Digital , is actively hiring a Lead RTL to GDS Engineer with deep expertise in block/subsystem-level physical design and signoff for advanced SoC designs (7nm and below). The role involves leading full RTL to GDSII implementation, owning delivery, mentoring junior engineers, and collaborating across functions. We’re looking for professionals who are passionate about driving execution quality, solving complex physical design challenges, and making impactful contributions in high-performance silicon projects. Key Skills & Responsibilities: Technical Responsibilities: Lead end-to-end RTL to GDSII implementation at block/subsystem level. Perform synthesis, floorplanning, placement, CTS, routing, and optimization for PPA. Full signoff closure experience including: Static Timing Analysis (STA) Physical Verification (DRC/LVS using Calibre) IR drop, Electromigration (EM), Crosstalk Drive low power design closure using UPF/CPF flows . Debug and resolve complex design and convergence issues. Collaborate with RTL, DFT, verification, and packaging teams for integration and handoff. Guide flow/methodology improvements and automation scripting (TCL, Python, Perl). Leadership Responsibilities: Provide technical leadership and mentorship to junior engineers. Conduct design reviews and drive quality across the team. Interact with program managers and cross-functional teams to ensure timely delivery. Key Skills: RTL to GDSII implementation Block & Subsystem level design STA (PrimeTime/Tempus) Synthesis (Design Compiler/Fusion Compiler) Place & Route (ICC2, Innovus) Calibre DRC/LVS RedHawk / Voltus (IR/EM analysis) Low power design (UPF/CPF) Scripting (TCL, Python, Perl) Tape-out experience at advanced nodes (7nm, 5nm, 3nm) Team leadership & technical mentoring Preferred Experience: Experience with TSMC, Samsung, Intel process nodes. Hands-on tape-out experience at FinFET nodes (5nm and below). Background in SoC integration and hierarchical design. Why Join Wafer Space – an ACL Digital Group? Work on cutting-edge SoC designs and the latest technology nodes. Be part of a highly technical and collaborative team. Best-in-industry compensation and growth opportunities. Lead from the front and make a real impact in semiconductor innovation. If this opportunity isn’t for you, please share or refer someone in your network who would be a great fit. Referrals are highly appreciated! (prabhu.p@acldigital.com)

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Physical Design Planning. Experience3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Physical Design Planning. Experience3-5 Years.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 6-12 years of experience in physical design from product-based/EDA companies. DDRPhy /PCIE-high speed interface PD Timing Signoff experience with SNPS/CDNS tools PDNIR signoff and Physical verification knowledge Automation skills python/Perl/TCL RDL-design + Bump Spec understanding for smooth SoC PDN integration and signoff Proficiency in automation to drive improvements in PPA Experience working on multiple technology nodes in advanced processes. Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating. Familiarity with ASIC design flows and physical design methodologies. Good to Have: Design level knowledge to optimize the implementation for PPPA Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.