357 Placement Jobs - Page 15

• Rostering of Faculty, Resource Utilization (Classroom and Faculty), • Batch Formation, Facilitating Monthly Faculty Meet, • Course ware distribution, Student Grooming Check • Coordination with all departments • Supporting Placement related activities Roles and Responsibilities • Rostering of Faculty, Resource Utilization (Classroom and Faculty), • Batch Formation, Facilitating Monthly Faculty Meet, • Course ware distribution, Student Grooming Check • Coordination with all departments • Supporting Placement related activities

This role does design and layout of complex VLSI (very large scale integration) circuits using graphic editing tools in cutting edge technological nodes. A major portion of the job is in creation of new physical design data from concepts, partial schematics or a working knowledge of overall requirements. Responsibilities include checking the design integrity with respect to semiconductor ground rules and the logical function of the circuit. Symbolic circuit data (schematics) are converted to physical shapes which represent the semiconductor process. The role ranges from manual shapes and checking tool manipulations to extended team coordination and methodology creation. The employee guides functional objectives or technologies. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 6-8 Years of relevant experience in Memory Layout design for blocks like Caches, CAMs, Register files, multiport register Files, Compilers etc.Should be in a position to work hands on on memory IPs, help generate and curate new ideas for layout designing, innovate new ways of layout designing, bring leadership into work and have growth mindset and have openmindedness to automation ideas; Excellent communication skills to be able to work with crosssite designers, EDA for development and curation of new tools needed for work. Should be able to understand various memory architechtures, experience in bit cells layouts, compiler layout design; Should have hands on experience in Finfets, GAA etc. Should have had experience in technology nodes below 7nm; LVS, DRC, Antenna, DFM, EM, IR, Methodology check debugging and fixing is a must; Leadership to drive collaborative initiatives with cross teams; SRAM designing experience is an added advantage Preferred technical and professional experience Scripting to ease deliverables is an added advantage. Automation skills in PERL, Python ,SKILL and/or TCL Environment: Professional knowledge related to incumbent's function/business unit and its processes.Communication/Negotiation: Advise other professionals. Effectively utilize group dynamics. Negotiate to define approaches and goals.Problem Solving: Recognize complex problems related to functional objectives. Analyze situations and implement solutions, or develop new system elements, procedures or processes. Creativity and judgment applied to developmental work on different projects within the business environment. Contribution/Leadership:Provides ongoing technical /operational guidance to lead professional work teams, conducts special projects, or manages department(s) (national or international). Understand department/ functional mission and vision. Defines and decides objectives within specified business concept or project and may have responsibility for tools and assigned resources. Utilizes expertise to directly influence people outside department or function. Sometimes no precedent exists.Impact on Business/Scope:Accountable for department results and for activities and/or projects involving multi-functional teams. Regularly participates in overall functional program planning. Activities are subject to business measurements, impact customer satisfaction, and impact project costs or expenses.

Develop and maintain relationships with a wide range of employers to understand their hiring needs and identify potential job opportunities for our candidates. - Work closely with our training team to identify the skills and strengths of each candidate and match them with suitable job openings. - Coordinate all aspects of the placement process, including resume submission, interview scheduling, and job offer negotiation. - Provide guidance and support to candidates throughout the job search and interview process, helping them prepare for interviews and assisting with any challenges they may face. - Monitor and track the performance and satisfaction of placed candidates in their new roles, and provide ongoing support to ensure their success. - Collaborate with other team members to continually improve our placement process, including gathering feedback from candidates and employers, and implementing changes as needed. Skills and Qualifications: - Bachelor's degree in business, human resources, or a related field. - Minimum of 3 years of experience in recruitment, talent acquisition, or placement. - Strong communication and networking skills, with the ability to build and maintain relationships with employers and candidates. - Excellent organizational and time management abilities, with a keen attention to detail. - A passion for helping others succeed in their careers and a genuine desire to make a positive impact in people's lives. - Familiarity with the latest trends and best practices in the placement industry. Roles and Responsibilities Strategic Planning: A Placement Manager is responsible for developing and implementing strategic plans to guide the placement activities within the organization. This involves understanding the current job market, identifying potential placement opportunities, and developing strategies to match qualified candidates with suitable job openings. 2. Relationship Building: Building and maintaining relationships with both clients and candidates is an essential aspect of the Placement Manager's role. This includes engaging with potential employers to understand their hiring needs and working closely with candidates to assess their skills, experiences, and career aspirations. 3. Recruitment and Selection: The Placement Manager is responsible for managing the entire recruitment and selection process. This involves sourcing and attracting qualified candidates, conducting interviews, and coordinating with hiring managers to facilitate the selection process. 4. Candidate Support: Providing support and guidance to candidates throughout the job search process is a critical responsibility. This involves offering career advice, resume writing assistance, interview preparation, and ongoing support to ensure a successful placement. 5. Compliance and Documentation: Adhering to all legal and compliance requirements related to recruitment and placement is essential. The Placement Manager is responsible for ensuring that all necessary documentation, including contracts, agreements, and employment offers, is completed accurately and in compliance with relevant laws and regulations. 6. Performance Management: Once a candidate is placed, the Placement Manager is responsible for monitoring their performance and ensuring that both the candidate and the employer are satisfied with the placement. This may involve conducting performance reviews, addressing any issues that arise, and providing ongoing support to ensure long-term success. 7. Reporting and Analysis: The Placement Manager is responsible for tracking placement metrics and analyzing data to assess the effectiveness of placement strategies. This information is used to make informed decisions and improvements in the placement process. 8. Continuous Improvement: Continuously improving the placement process and staying updated on industry trends and best practices is essential. The Placement Manager should actively seek out new opportunities, technologies, and strategies to enhance the overall placement process.

Responsibilities The India System design team is responsible to own and deliver System design milestones for IBM POWER and mainframe platforms. The team collaborates with Global System design & development teams and stakeholders. As a Physical Design Engineer for PCB, the candidate must have experience to deliver complete custom PCB card designs, which would be used for our hardware products. Responsibilities As Physical Design Engineer, the responsibilities include Work with Card Logic Design and Card Signal Integrity Engineers to deliver complete custom PCB card designs. Implement feedback from bring up efforts for modifications to existing card layouts. Work in the Cadence design space to layout, wire multi-layer PCB designs. Create EC list of changes from one release to the next. Lead Physical Design reviews to support Gerber release schedules Generate and maintain documentation for PCB card designs Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Bachelors in Electrical/Electronics Engineering Experience with CAD tools for PCB design Programming experience (Python, SKILL, etc.) Preferred technical and professional experience Familiarity with server design and architecture. Experience with Cadence tools for PCB design Experience with PCB fabrication processes Multi-disciplinary engineering experience (Mechanical, Thermal, etc.) Experience with Git, GitHub, or other software repository versioning tools

Responsibilities 1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness andparasitic optimisations 3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. 4. Participate in building and enhancing layout flow for faster, higher quality design process. 5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks 6. Collaborate with Circuit Designers to solve challenging problems 7. Writing SKILL/PYTHON scripts to automate repetitive tasks 8. Work with Place and Route engineer to integrate custom macros into top level. 9. Able to perform design reviews across global team 10. Work closely with required global teams to ensure the success of the whole product. 11. Leadership in delivery of macros we plan to own from India Job requirements: 1. Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers etc. 2. Experience in designing layouts for high-speed circuits is a plus. 3. Layout experience in the following technology nodes:3nm, 5nm and 7nm FinFET. 4. Good team worker with multi-discipline, multi-cultural and multi-site environments 5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms 6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions 7. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise The Analog layout design engineer with experience in next generation Ultra high speed serial IO link (HSS) interface for Cognitive, ML,DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high speed 32G/50G/112G IO link interfaces. Preferred technical and professional experience Experience in 7 and 14 nm analog layout design. Working on Cutting edge technology and HSS domain . Quick learner, deep layout design knowledge, problem solving skills and good communication skills with cross teams across the Geos.

Responsibilities In this role, you are expected to Efficient in LVS/DRC Runset development Hands on experience in working on LVS and DRC runset development and support Knowledge/Exposure in lower process node Have excellent debugging skills. Have strong interpersonal skills needed to coordinate deliverables and requirements from several areas within and outside of the organisation. Have familiarity with ICV , Calibre Physical Design Verification Tools Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 2-5 years of Chip Layout and Runset Coding (ICV / Calibre ) Chip layout fundamentals (understanding the layers and how they connect and the rules on sizing and spacing and the electrical connectivity logic) Runset coding in general, ICV pxl in particular Basic SKILL code (for interfacing with Virtuoso) Basic TCL for interfacing with Custom Compiler and ICV Basic Python scripting VLSI knowledge Proven problem-solving skills and the ability to work in a team environment are a must EDA tool development experience Preferred technical and professional experience Cadence,Synopsys,VLSI Knowledge

Responsibilities 1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness andparasitic optimisations 3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. 4. Participate in building and enhancing layout flow for faster, higher quality design process. 5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks 6. Collaborate with Circuit Designers to solve challenging problems 7. Writing SKILL/PYTHON scripts to automate repetitive tasks 8. Work with Place and Route engineer to integrate custom macros into top level. 9. Able to perform design reviews across global team 10. Work closely with required global teams to ensure the success of the whole product. 11. Leadership in delivery of macros we plan to own from India Job requirements: 1. Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers etc. 2. Experience in designing layouts for high-speed circuits is a plus. 3. Layout experience in the following technology nodes:3nm, 5nm and 7nm FinFET. 4. Good team worker with multi-discipline, multi-cultural and multi-site environments 5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms 6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions7. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise The Analog layout design engineer with experience in next generation Ultra high speed serial IO link (HSS) interface for Cognitive, ML,DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high speed 32G/50G/112G IO link interfaces. Preferred technical and professional experience Experience in 7 and 14 nm analog layout design. Working on Cutting edge technology and HSS domain . Quick learner, deep layout design knowledge, problem solving skills and good communication skills with cross teams across the Geos.