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0.0 years
0 Lacs
bengaluru, karnataka, india
On-site
Role : Sr Physical Design Lead/BE Integration This position is for senior level engineer Full Chip Physical Design/Integrations/ SoC Floor planning/Bump Planning/ Pin Assignments /Feed through/ LFU Optimization/Physical Verification, Power design/implementation/signoff. He must have hands on Physical Design experience and must have handled RTL to GDS II at Top level Key Responsibilities: Expertise in hierarchical RTL2GDSII design implementation Expertise in pin assignment, Power planning, IO/Bump Planning, Pad Ring Creation, Die File Creation, RDL Routing, working with Package Team for Optimize the Bumps Full chip Hierarchical Floor Planning, Block planning , block level constraints, hierarc...
Posted 6 days ago
3.0 - 7.0 years
0 Lacs
telangana
On-site
Role Overview: As an Electrical Design Engineer (FPGA Logic Design) at Micron Technology, you will be responsible for designing, developing, and implementing FPGA and/or SoC solutions for advanced semiconductor manufacturing test equipment. Your role will involve deriving specifications, developing modules, debugging RTL code, performing synthesis and static timing analysis, generating verification test plans, collaborating with cross-functional teams, and supporting PCB layout and verification. Your contributions will lead to innovative test solutions and improved system performance. Key Responsibilities: - Derive FPGA and SoC design specifications from system requirements - Develop modules...
Posted 1 week ago
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